diff --git a/Source/DSPSpy/DSPSpy.vcproj b/Source/DSPSpy/DSPSpy.vcproj
index ce4e2fc9e8..46797ee9da 100644
--- a/Source/DSPSpy/DSPSpy.vcproj
+++ b/Source/DSPSpy/DSPSpy.vcproj
@@ -114,14 +114,6 @@
 	<References>
 	</References>
 	<Files>
-		<File
-			RelativePath=".\asm.h"
-			>
-		</File>
-		<File
-			RelativePath=".\color.h"
-			>
-		</File>
 		<File
 			RelativePath=".\Config.h"
 			>
@@ -138,14 +130,6 @@
 			RelativePath=".\display_font.cpp"
 			>
 		</File>
-		<File
-			RelativePath=".\dsp.h"
-			>
-		</File>
-		<File
-			RelativePath=".\irq.h"
-			>
-		</File>
 		<File
 			RelativePath=".\main_spy.cpp"
 			>
@@ -162,10 +146,6 @@
 			RelativePath=".\mem_dump.h"
 			>
 		</File>
-		<File
-			RelativePath=".\processor.h"
-			>
-		</File>
 		<File
 			RelativePath=".\Stubs.cpp"
 			>
diff --git a/Source/DSPSpy/asm.h b/Source/DSPSpy/asm.h
deleted file mode 100644
index 7f948c8583..0000000000
--- a/Source/DSPSpy/asm.h
+++ /dev/null
@@ -1,317 +0,0 @@
-#ifndef __ASM_H__
-#define __ASM_H__
-
-#ifdef _LANGUAGE_ASSEMBLY
-/* Condition Register Bit Fields */
-
-#define	cr0	0
-#define	cr1	1
-#define	cr2	2
-#define	cr3	3
-#define	cr4	4
-#define	cr5	5
-#define	cr6	6
-#define	cr7	7
-
-
-/* General Purpose Registers (GPRs) */
-
-#define	r0	0
-#define	r1	1
-#define	sp	1
-#define	r2	2
-#define	toc	2
-#define	r3	3
-#define	r4	4
-#define	r5	5
-#define	r6	6
-#define	r7	7
-#define	r8	8
-#define	r9	9
-#define	r10	10
-#define	r11	11
-#define	r12	12
-#define	r13	13
-#define	r14	14
-#define	r15	15
-#define	r16	16
-#define	r17	17
-#define	r18	18
-#define	r19	19
-#define	r20	20
-#define	r21	21
-#define	r22	22
-#define	r23	23
-#define	r24	24
-#define	r25	25
-#define	r26	26
-#define	r27	27
-#define	r28	28
-#define	r29	29
-#define	r30	30
-#define	r31	31
-
-
-/* Floating Point Registers (FPRs) */
-
-#define	fr0		0
-#define	fr1		1
-#define	fr2		2
-#define	fr3		3
-#define	fr4		4
-#define	fr5		5
-#define	fr6		6
-#define	fr7		7
-#define	fr8		8
-#define	fr9		9
-#define	fr10	10
-#define	fr11	11
-#define	fr12	12
-#define	fr13	13
-#define	fr14	14
-#define	fr15	15
-#define	fr16	16
-#define	fr17	17
-#define	fr18	18
-#define	fr19	19
-#define	fr20	20
-#define	fr21	21
-#define	fr22	22
-#define	fr23	23
-#define	fr24	24
-#define	fr25	25
-#define	fr26	26
-#define	fr27	27
-#define	fr28	28
-#define	fr29	29
-#define	fr30	30
-#define	fr31	31
-
-#define	vr0		0
-#define	vr1		1
-#define	vr2		2
-#define	vr3		3
-#define	vr4		4
-#define	vr5		5
-#define	vr6		6
-#define	vr7		7
-#define	vr8		8
-#define	vr9		9
-#define	vr10	10
-#define	vr11	11
-#define	vr12	12
-#define	vr13	13
-#define	vr14	14
-#define	vr15	15
-#define	vr16	16
-#define	vr17	17
-#define	vr18	18
-#define	vr19	19
-#define	vr20	20
-#define	vr21	21
-#define	vr22	22
-#define	vr23	23
-#define	vr24	24
-#define	vr25	25
-#define	vr26	26
-#define	vr27	27
-#define	vr28	28
-#define	vr29	29
-#define	vr30	30
-#define	vr31	31
-
-#define SPRG0	272
-#define SPRG1	273
-#define SPRG2	274
-#define SPRG3	275
-
-#define PMC1    953
-#define PMC2    954
-#define PMC3    957
-#define PMC4    958
-
-#define MMCR0	952
-#define MMCR1	956
-
-
-#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
-#define EXCEPTION_NUMBER 8
-#define SRR0_OFFSET 12
-#define SRR1_OFFSET 16
-#define GPR0_OFFSET 20
-#define GPR1_OFFSET 24
-#define GPR2_OFFSET 28
-#define GPR3_OFFSET 32
-#define GPR4_OFFSET 36
-#define GPR5_OFFSET 40
-#define GPR6_OFFSET 44
-#define GPR7_OFFSET 48
-#define GPR8_OFFSET 52
-#define GPR9_OFFSET 56
-#define GPR10_OFFSET 60
-#define GPR11_OFFSET 64
-#define GPR12_OFFSET 68
-#define GPR13_OFFSET 72
-#define GPR14_OFFSET 76
-#define GPR15_OFFSET 80
-#define GPR16_OFFSET 84
-#define GPR17_OFFSET 88
-#define GPR18_OFFSET 92
-#define GPR19_OFFSET 96
-#define GPR20_OFFSET 100
-#define GPR21_OFFSET 104
-#define GPR22_OFFSET 108
-#define GPR23_OFFSET 112
-#define GPR24_OFFSET 116
-#define GPR25_OFFSET 120
-#define GPR26_OFFSET 124
-#define GPR27_OFFSET 128
-#define GPR28_OFFSET 132
-#define GPR29_OFFSET 136
-#define GPR30_OFFSET 140
-#define GPR31_OFFSET 144
-
-#define GQR0_OFFSET 148
-#define GQR1_OFFSET 152
-#define GQR2_OFFSET 156
-#define GQR3_OFFSET 160
-#define GQR4_OFFSET 164
-#define GQR5_OFFSET 168
-#define GQR6_OFFSET 172
-#define GQR7_OFFSET 176
-
-#define CR_OFFSET	 180
-#define LR_OFFSET	 184
-#define CTR_OFFSET	 188
-#define XER_OFFSET	 192
-#define MSR_OFFSET	 196
-#define DAR_OFFSET	 200
-
-#define	STATE_OFFSET 204
-#define MODE_OFFSET	 206
-	 
-#define FPR0_OFFSET	208
-#define FPR1_OFFSET 216
-#define FPR2_OFFSET 224
-#define FPR3_OFFSET 232
-#define FPR4_OFFSET 240
-#define FPR5_OFFSET 248
-#define FPR6_OFFSET 256
-#define FPR7_OFFSET 264
-#define FPR8_OFFSET 272
-#define FPR9_OFFSET 280
-#define FPR10_OFFSET 288
-#define FPR11_OFFSET 296
-#define FPR12_OFFSET 304
-#define FPR13_OFFSET 312
-#define FPR14_OFFSET 320
-#define FPR15_OFFSET 328
-#define FPR16_OFFSET 336
-#define FPR17_OFFSET 344
-#define FPR18_OFFSET 352
-#define FPR19_OFFSET 360
-#define FPR20_OFFSET 368
-#define FPR21_OFFSET 376
-#define FPR22_OFFSET 384
-#define FPR23_OFFSET 392
-#define FPR24_OFFSET 400
-#define FPR25_OFFSET 408
-#define FPR26_OFFSET 416
-#define FPR27_OFFSET 424
-#define FPR28_OFFSET 432
-#define FPR29_OFFSET 440
-#define FPR30_OFFSET 448
-#define FPR31_OFFSET 456
-
-#define FPSCR_OFFSET 464
-
-#define PSR0_OFFSET 472
-#define PSR1_OFFSET 480
-#define PSR2_OFFSET 488
-#define PSR3_OFFSET 496
-#define PSR4_OFFSET 504
-#define PSR5_OFFSET 512
-#define PSR6_OFFSET 520
-#define PSR7_OFFSET 528
-#define PSR8_OFFSET 536
-#define PSR9_OFFSET 544
-#define PSR10_OFFSET 552
-#define PSR11_OFFSET 560
-#define PSR12_OFFSET 568
-#define PSR13_OFFSET 576
-#define PSR14_OFFSET 584
-#define PSR15_OFFSET 592
-#define PSR16_OFFSET 600
-#define PSR17_OFFSET 608
-#define PSR18_OFFSET 616
-#define PSR19_OFFSET 624
-#define PSR20_OFFSET 632
-#define PSR21_OFFSET 640
-#define PSR22_OFFSET 648
-#define PSR23_OFFSET 656
-#define PSR24_OFFSET 664
-#define PSR25_OFFSET 672
-#define PSR26_OFFSET 680
-#define PSR27_OFFSET 688
-#define PSR28_OFFSET 696
-#define PSR29_OFFSET 704
-#define PSR30_OFFSET 712
-#define PSR31_OFFSET 720
-/*
- * maintain the EABI requested 8 bytes aligment
- * As SVR4 ABI requires 16, make it 16 (as some
- * exception may need more registers to be processed...)
- */
-#define EXCEPTION_FRAME_END 728
-
-#define	IBAT0U		528
-#define	IBAT0L		529	
-#define	IBAT1U		530	
-#define	IBAT1L		531	
-#define	IBAT2U		532	
-#define	IBAT2L		533	
-#define	IBAT3U		534	
-#define	IBAT3L		535	
-
-#define	DBAT0U		536
-#define	DBAT0L		537	
-#define	DBAT1U		538	
-#define	DBAT1L		538	
-#define	DBAT2U		540	
-#define	DBAT2L		541	
-#define	DBAT3U		542	
-#define	DBAT3L		543
-
-#define HID0		1008
-#define HID1		1009
-#define HID2		920	
-
-#define GQR0		912
-#define GQR1		913
-#define GQR2		914
-#define GQR3		915
-#define GQR4		916
-#define GQR5		917
-#define GQR6		918
-#define GQR7		919
-
-#define L2CR		1017
-
-#define DMAU		922
-#define DMAL		923
-
-#endif		//_LANGUAGE_ASSEMBLY
-
-#define MSR_RI				0x00000002
-#define MSR_DR				0x00000010
-#define MSR_IR				0x00000020
-#define MSR_IP				0x00000040
-#define MSR_SE				0x00000400
-#define MSR_ME				0x00001000
-#define MSR_FP				0x00002000
-#define MSR_POW				0x00004000
-#define MSR_EE				0x00008000
-
-#define PPC_ALIGNMENT		4
-
-#endif		//__ASM_H__
diff --git a/Source/DSPSpy/color.h b/Source/DSPSpy/color.h
deleted file mode 100644
index 5f70935a11..0000000000
--- a/Source/DSPSpy/color.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __COLOR_H__
-#define __COLOR_H__
-
-// luminance is stored twice, thus one of the lum. is
-// redundant, but this way we can fill the screen.
-
-#define COLOR_BLACK        (0x00800080)
-#define COLOR_MAROON       (0x266A26C0)
-#define COLOR_GREEN        (0x4B554B4A)
-#define COLOR_OLIVE        (0x7140718A)
-#define COLOR_NAVY         (0x0EC00E75)
-#define COLOR_PURPLE       (0x34AA34B5)
-#define COLOR_TEAL         (0x59955940)
-#define COLOR_GRAY         (0x80808080)
-#define COLOR_SILVER       (0xC080C080)
-#define COLOR_RED          (0x4C544CFF)
-#define COLOR_LIME         (0x952B9515)
-#define COLOR_YELLOW       (0xE100E194)
-#define COLOR_BLUE         (0x1DFF1D6B)
-#define COLOR_FUCHSIA      (0x69D469EA)
-#define COLOR_AQUA         (0xB2ABB200)
-#define COLOR_WHITE        (0xFF80FF80)
-#define COLOR_MONEYGREEN   (0xD076D074)
-#define COLOR_SKYBLUE      (0xC399C36A)
-#define COLOR_CREAM        (0xFA79FA82)
-#define COLOR_MEDGRAY      (0xA082A07F)
-
-#endif /* COLOR_H */
diff --git a/Source/DSPSpy/display.cpp b/Source/DSPSpy/display.cpp
index 409dd5628c..808711e1b8 100644
--- a/Source/DSPSpy/display.cpp
+++ b/Source/DSPSpy/display.cpp
@@ -8,9 +8,9 @@
 #undef errno
 extern int errno;
 
-#include "asm.h"
-#include "processor.h"
-#include "color.h"
+#include <ogc/color.h>
+#include <ogc/machine/asm.h>
+#include <ogc/machine/processor.h>
 
 #define FONT_XSIZE			8
 #define FONT_YSIZE			16
diff --git a/Source/DSPSpy/dsp.h b/Source/DSPSpy/dsp.h
deleted file mode 100644
index 87062c5e90..0000000000
--- a/Source/DSPSpy/dsp.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef __DSP_H__
-#define __DSP_H__
-
-#include <gctypes.h>
-
-#define DSPTASK_INIT		0
-#define DSPTASK_RUN			1
-#define DSPTASK_YIELD		2
-#define DSPTASK_DONE		3
-
-#define DSPTASK_CLEARALL	0x00000000
-#define DSPTASK_ATTACH		0x00000001
-#define DSPTASK_CANCEL		0x00000002
-
-#ifdef __cplusplus
-   extern "C" {
-#endif /* __cplusplus */
-
-typedef void (*DSPCallback)(void *task);
-
-typedef struct _dsp_task {
-	vu32 state;
-	vu32 prio;
-	vu32 flags;
-	
-	u16 init_vec;
-	u16 resume_vec;
-	
-	u16 *iram_maddr;
-	u32 iram_len;
-	u16 iram_addr;
-
-	u16 *dram_maddr;
-	u32 dram_len;
-	u16 dram_addr;
-	
-	DSPCallback init_cb;
-	DSPCallback res_cb;
-	DSPCallback done_cb;
-	DSPCallback req_cb;
-
-	struct _dsp_task *next;
-	struct _dsp_task *prev;
-} dsptask_t;
-
-void DSP_Init();
-u32 DSP_CheckMailTo();
-u32 DSP_CheckMailFrom();
-u32 DSP_ReadMailFrom();
-void DSP_AssertInt();
-void DSP_SendMailTo(u32 mail);
-u32 DSP_ReadCPUtoDSP();
-dsptask_t* DSP_AddTask(dsptask_t *task);
-
-#ifdef __cplusplus
-   }
-#endif /* __cplusplus */
-
-#endif
diff --git a/Source/DSPSpy/irq.h b/Source/DSPSpy/irq.h
deleted file mode 100644
index 738f1fbfd1..0000000000
--- a/Source/DSPSpy/irq.h
+++ /dev/null
@@ -1,97 +0,0 @@
-#ifndef __IRQ_H__
-#define __IRQ_H__
-
-#include <gctypes.h>
-#include "context.h"
-
-#define IM_NONE				 (0x00000000)
-#define IRQ_MEM0			 0
-#define IRQ_MEM1			 1
-#define IRQ_MEM2			 2
-#define IRQ_MEM3			 3
-#define IRQ_MEMADDRESS		 4
-#define IRQ_DSP_AI			 5
-#define IRQ_DSP_ARAM		 6
-#define IRQ_DSP_DSP			 7
-#define IRQ_AI_AI			 8
-#define IRQ_EXI0_EXI		 9
-#define IRQ_EXI0_TC			 10
-#define IRQ_EXI0_EXT		 11
-#define IRQ_EXI1_EXI		 12
-#define IRQ_EXI1_TC			 13
-#define IRQ_EXI1_EXT		 14
-#define IRQ_EXI2_EXI		 15
-#define IRQ_EXI2_TC			 16
-#define IRQ_PI_CP			 17
-#define IRQ_PI_PETOKEN		 18
-#define IRQ_PI_PEFINISH		 19
-#define IRQ_PI_SI			 20
-#define IRQ_PI_DI			 21
-#define IRQ_PI_RSW			 22
-#define IRQ_PI_ERROR		 23
-#define IRQ_PI_VI			 24
-#define IRQ_PI_DEBUG		 25
-#define IRQ_PI_HSP			 26
-#define IRQ_MAX				 32
-
-#define IRQMASK(irq)		 (0x80000000u>>irq)
-
-#define IM_MEM0				 IRQMASK(IRQ_MEM0)
-#define IM_MEM1				 IRQMASK(IRQ_MEM1)
-#define IM_MEM2				 IRQMASK(IRQ_MEM2)
-#define IM_MEM3				 IRQMASK(IRQ_MEM3)
-#define IM_MEMADDRESS		 IRQMASK(IRQ_MEMADDRESS)
-#define IM_MEM				 (IM_MEM0|IM_MEM1|IM_MEM2|IM_MEM3|IM_MEMADDRESS)
-
-#define IM_DSP_AI			 IRQMASK(IRQ_DSP_AI)
-#define IM_DSP_ARAM			 IRQMASK(IRQ_DSP_ARAM)
-#define IM_DSP_DSP			 IRQMASK(IRQ_DSP_DSP)
-#define IM_DSP				 (IM_DSP_AI|IM_DSP_ARAM|IM_DSP_DSP)
-
-#define IM_AI_AI			 IRQMASK(IRQ_AI_AI)
-#define IM_AI				 (IRQ_AI_AI)
-
-#define IM_EXI0_EXI			 IRQMASK(IRQ_EXI0_EXI)
-#define IM_EXI0_TC			 IRQMASK(IRQ_EXI0_TC)
-#define IM_EXI0_EXT			 IRQMASK(IRQ_EXI0_EXT)
-#define IM_EXI0				 (IM_EXI0_EXI|IM_EXI0_TC|IM_EXI0_EXT)
-
-#define IM_EXI1_EXI			 IRQMASK(IRQ_EXI1_EXI)
-#define IM_EXI1_TC			 IRQMASK(IRQ_EXI1_TC)
-#define IM_EXI1_EXT			 IRQMASK(IRQ_EXI1_EXT)
-#define IM_EXI1				 (IM_EXI1_EXI|IM_EXI1_TC|IM_EXI1_EXT)
-
-#define IM_EXI2_EXI			 IRQMASK(IRQ_EXI2_EXI)
-#define IM_EXI2_TC			 IRQMASK(IRQ_EXI2_TC)
-#define IM_EXI2				 (IM_EXI2_EXI|IM_EXI2_TC)
-#define IM_EXI				 (IM_EXI0|IM_EXI1|IM_EXI2)
-
-#define IM_PI_CP			 IRQMASK(IRQ_PI_CP)
-#define IM_PI_PETOKEN		 IRQMASK(IRQ_PI_PETOKEN)
-#define IM_PI_PEFINISH		 IRQMASK(IRQ_PI_PEFINISH)
-#define IM_PI_SI			 IRQMASK(IRQ_PI_SI)
-#define IM_PI_DI			 IRQMASK(IRQ_PI_DI)
-#define IM_PI_RSW			 IRQMASK(IRQ_PI_RSW)
-#define IM_PI_ERROR			 IRQMASK(IRQ_PI_ERROR)
-#define IM_PI_VI			 IRQMASK(IRQ_PI_VI)
-#define IM_PI_DEBUG			 IRQMASK(IRQ_PI_DEBUG)
-#define IM_PI_HSP			 IRQMASK(IRQ_PI_HSP)
-#define IM_PI				 (IM_PI_CP|IM_PI_PETOKEN|IM_PI_PEFINISH|IM_PI_SI|IM_PI_DI|IM_PI_RSW|IM_PI_ERROR|IM_PI_VI|IM_PI_DEBUG|IM_PI_HSP)
-
-#ifdef __cplusplus
-   extern "C" {
-#endif /* __cplusplus */
-
-typedef void (raw_irq_handler_t)(u32,void *);
-
-raw_irq_handler_t* IRQ_Request(u32 nIrq,raw_irq_handler_t *pHndl,void *pCtx);
-raw_irq_handler_t* IRQ_Free(u32 nIrq);
-raw_irq_handler_t* IRQ_GetHandler(u32 nIrq);
-u32 IRQ_Disable();
-void IRQ_Restore(u32 level);
-
-#ifdef __cplusplus
-   }
-#endif /* __cplusplus */
-
-#endif
diff --git a/Source/DSPSpy/main_spy.cpp b/Source/DSPSpy/main_spy.cpp
index c54b135256..9569d29ae3 100644
--- a/Source/DSPSpy/main_spy.cpp
+++ b/Source/DSPSpy/main_spy.cpp
@@ -10,19 +10,18 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <network.h>
 #include <ogcsys.h>
 #include <time.h>
 #include <fat.h>
 #include <fcntl.h>
+#include <ogc/color.h>
+#include <ogc/dsp.h>
+#include <ogc/irq.h>
+#include <ogc/machine/asm.h>
+#include <ogc/machine/processor.h>
 #include <wiiuse/wpad.h>
 
-#include "color.h"
-#include "network.h"
-#include "dsp.h"
-#include "asm.h"
-#include "processor.h"
-#include "irq.h"
-#include "dsp.h"
 #include "display.h"
 
 // Pull in some constants etc from DSPCore.
diff --git a/Source/DSPSpy/processor.h b/Source/DSPSpy/processor.h
deleted file mode 100644
index 68da9175a1..0000000000
--- a/Source/DSPSpy/processor.h
+++ /dev/null
@@ -1,98 +0,0 @@
-#ifndef __PROCESSOR_H__
-#define __PROCESSOR_H__
-
-#include <gctypes.h>
-
-#define __stringify(rn)					#rn
-#define ATTRIBUTE_ALIGN(v)				__attribute__((aligned(v)))
-
-#define ppcsync() asm volatile("sc")
-#define ppchalt() ({					\
-	asm volatile("sync");				\
-	while(1) {							\
-		asm volatile("nop");			\
-		asm volatile("li 3,0");			\
-		asm volatile("nop");			\
-	}									\
-})
-
-#define mfdcr(_rn) ({register u32 _rval; \
-		asm volatile("mfdcr %0," __stringify(_rn) \
-             : "=r" (_rval)); _rval;})
-#define mtdcr(rn, val)  asm volatile("mtdcr " __stringify(rn) ",%0" : : "r" (val))
-
-#define mfmsr()   ({register u32 _rval; \
-		asm volatile("mfmsr %0" : "=r" (_rval)); _rval;})
-#define mtmsr(val)  asm volatile("mtmsr %0" : : "r" (val))
-
-#define mfdec()   ({register u32 _rval; \
-		asm volatile("mfdec %0" : "=r" (_rval)); _rval;})
-#define mtdec(_val)  asm volatile("mtdec %0" : : "r" (_val))
-
-#define mfspr(_rn) ({register u32 _rval; \
-		asm volatile("mfspr %0," __stringify(_rn) \
-             : "=r" (_rval)); _rval;})
-#define mtspr(_rn, _val)  asm volatile("mtspr " __stringify(_rn) ",%0" : : "r" (_val))
-
-#define mfwpar()		mfspr(921)
-#define mtwpar(_val)	mtspr(921,_val)
-
-#define mfmmcr0()		mfspr(952)
-#define mtmmcr0(_val)	mtspr(952,_val)
-#define mfmmcr1()		mfspr(956)
-#define mtmmcr1(_val)	mtspr(956,_val)
-
-#define mfpmc1()		mfspr(953)
-#define mtpmc1(_val)	mtspr(953,_val)
-#define mfpmc2()		mfspr(954)
-#define mtpmc2(_val)	mtspr(954,_val)
-#define mfpmc3()		mfspr(957)
-#define mtpmc3(_val)	mtspr(957,_val)
-#define mfpmc4()		mfspr(958)
-#define mtpmc4(_val)	mtspr(958,_val)
-
-#define cntlzw(_val) ({register u32 _rval; \
-					  asm volatile("cntlzw %0, %1" : "=r"((_rval)) : "r"((_val))); _rval;})
-
-#define _CPU_MSR_GET( _msr_value ) \
-  do { \
-    _msr_value = 0; \
-    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
-  } while (0)
-
-#define _CPU_MSR_SET( _msr_value ) \
-{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
-
-#define _CPU_ISR_Enable() \
-	{ register u32 _val = 0; \
-	  asm volatile ("mfmsr %0; ori %0,%0,0x8000; mtmsr %0" : \
-					"=&r" (_val) : "0" (_val));\
-	}
-
-#define _CPU_ISR_Disable( _isr_cookie ) \
-  { register u32 _disable_mask = MSR_EE; \
-    _isr_cookie = 0; \
-    asm volatile ( \
-	"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
-	"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
-	"0" ((_isr_cookie)), "1" ((_disable_mask)) \
-	); \
-  }
-
-#define _CPU_ISR_Restore( _isr_cookie )  \
-  { \
-     asm volatile ( "mtmsr %0" : \
-		   "=r" ((_isr_cookie)) : \
-                   "0" ((_isr_cookie))); \
-  }
-
-#define _CPU_ISR_Flash( _isr_cookie ) \
-  { register u32 _disable_mask = MSR_EE; \
-    asm volatile ( \
-      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
-      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
-      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
-    ); \
-  }
-
-#endif