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[AArch64] Optimization in the dispatcher.

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Align our dispatcher to a page so we can jump to it with a ADRP+BR pair instead of ADRP+ADD+BR.
Also make sure to save /all/ of our callee saved registers that we are supposed to save.
Requires PR #1705 prior to merging.
This commit is contained in:
Ryan Houdek 2014-12-19 21:42:21 -06:00
parent f4ab1443fa
commit 360cf761d2
1 changed files with 13 additions and 5 deletions
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18
Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
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@ -13,15 +13,24 @@ using namespace Arm64Gen;
void JitArm64AsmRoutineManager::Generate()
{
// This value is all of the callee saved registers that we are required to save.
// According to the AACPS64 we need to save R19 ~ R30.
const u32 ALL_CALLEE_SAVED = 0x7FF80000;
BitSet32 regs_to_save(ALL_CALLEE_SAVED);
enterCode = GetCodePtr();
SUB(SP, SP, 16);
STR(INDEX_UNSIGNED, X30, SP, 0);
ABI_PushRegisters(regs_to_save);
MOVI2R(X29, (u64)&PowerPC::ppcState);
FixupBranch to_dispatcher = B();
// If we align the dispatcher to a page then we can load its location with one ADRP instruction
AlignCodePage();
dispatcher = GetCodePtr();
printf("Dispatcher is %p\n", dispatcher);
WARN_LOG(DYNA_REC, "Dispatcher is %p\n", dispatcher);
SetJumpTarget(to_dispatcher);
// Downcount Check
// The result of slice decrementation should be in flags if somebody jumped here
// IMPORTANT - We jump on negative, not carry!!!
@ -77,8 +86,7 @@ void JitArm64AsmRoutineManager::Generate()
SetJumpTarget(Exit);
LDR(INDEX_UNSIGNED, X30, SP, 0);
ADD(SP, SP, 16);
ABI_PopRegisters(regs_to_save);
RET(X30);
FlushIcache();