mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-02-26 09:41:11 +00:00
Pierre Bourdon
commit
311caef094
@ -203,7 +203,7 @@ void OpArg::WriteRest(XEmitter *emit, int extraBytes, X64Reg _operandReg,
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{
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// Oh, RIP addressing.
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_offsetOrBaseReg = 5;
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emit->WriteModRM(0, _operandReg&7, 5);
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emit->WriteModRM(0, _operandReg, _offsetOrBaseReg);
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//TODO : add some checks
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#ifdef _M_X64
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u64 ripAddr = (u64)emit->GetCodePtr() + 4 + extraBytes;
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@ -327,7 +327,6 @@ void OpArg::WriteRest(XEmitter *emit, int extraBytes, X64Reg _operandReg,
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}
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}
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// W = operand extended width (1 if 64-bit)
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// R = register# upper bit
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// X = scale amnt upper bit
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@ -1390,6 +1389,10 @@ void XEmitter::PSRLQ(X64Reg reg, int shift) {
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Write8(shift);
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}
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void XEmitter::PSRLQ(X64Reg reg, OpArg arg) {
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WriteSSEOp(64, 0xd3, true, reg, arg);
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}
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void XEmitter::PSLLW(X64Reg reg, int shift) {
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WriteSSEOp(64, 0x71, true, (X64Reg)6, R(reg));
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Write8(shift);
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@ -1437,7 +1440,19 @@ void XEmitter::PSHUFB(X64Reg dest, OpArg arg) {
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Write8(0x0f);
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Write8(0x38);
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Write8(0x00);
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arg.WriteRest(this, 0);
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arg.WriteRest(this);
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}
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void XEmitter::PTEST(X64Reg dest, OpArg arg) {
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if (!cpu_info.bSSE4_1) {
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PanicAlert("Trying to use PTEST on a system that doesn't support it. Nobody hears your screams.");
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}
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Write8(0x66);
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Write8(0x0f);
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Write8(0x38);
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Write8(0x17);
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arg.operandReg = dest;
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arg.WriteRest(this);
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}
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void XEmitter::PAND(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xDB, true, dest, arg);}
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@ -1458,7 +1473,7 @@ void XEmitter::PADDUSW(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xDD, true, dest
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void XEmitter::PSUBB(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xF8, true, dest, arg);}
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void XEmitter::PSUBW(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xF9, true, dest, arg);}
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void XEmitter::PSUBD(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xFA, true, dest, arg);}
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void XEmitter::PSUBQ(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xDB, true, dest, arg);}
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void XEmitter::PSUBQ(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xFB, true, dest, arg);}
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void XEmitter::PSUBSB(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xE8, true, dest, arg);}
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void XEmitter::PSUBSW(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0xE9, true, dest, arg);}
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@ -1497,6 +1512,8 @@ void XEmitter::VSUBSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64,
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void XEmitter::VMULSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64, sseMUL, false, regOp1, regOp2, arg);}
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void XEmitter::VDIVSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64, sseDIV, false, regOp1, regOp2, arg);}
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void XEmitter::VSQRTSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64, sseSQRT, false, regOp1, regOp2, arg);}
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void XEmitter::VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64, sseAND, false, regOp1, regOp2, arg);}
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void XEmitter::VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64, sseANDN, false, regOp1, regOp2, arg);}
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// Prefixes
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@ -1509,6 +1526,25 @@ void XEmitter::FWAIT()
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Write8(0x9B);
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}
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// TODO: make this more generic
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void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, OpArg arg)
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{
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int mf = 0;
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switch (bits) {
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case 32: mf = 0; break;
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case 64: mf = 2; break;
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default: _assert_msg_(DYNA_REC, 0, "WriteFloatLoadStore: bits is not 32 or 64");
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}
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Write8(0xd9 | (mf << 1));
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// x87 instructions use the reg field of the ModR/M byte as opcode:
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arg.WriteRest(this, 0, (X64Reg) op);
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}
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void XEmitter::FLD(int bits, OpArg src) {WriteFloatLoadStore(bits, floatLD, src);}
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void XEmitter::FST(int bits, OpArg dest) {WriteFloatLoadStore(bits, floatST, dest);}
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void XEmitter::FSTP(int bits, OpArg dest) {WriteFloatLoadStore(bits, floatSTP, dest);}
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void XEmitter::FNSTSW_AX() { Write8(0xDF); Write8(0xE0); }
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void XEmitter::RTDSC() { Write8(0x0F); Write8(0x31); }
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// helper routines for setting pointers
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@ -100,6 +100,12 @@ enum NormalOp {
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nrmXCHG,
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};
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enum FloatOp {
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floatLD = 0,
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floatST = 2,
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floatSTP = 3,
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};
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class XEmitter;
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// RIP addressing does not benefit from micro op fusion on Core arch
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@ -118,6 +124,7 @@ struct OpArg
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void WriteRex(XEmitter *emit, int opBits, int bits, int customOp = -1) const;
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void WriteVex(XEmitter* emit, int size, int packed, Gen::X64Reg regOp1, X64Reg regOp2) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=(X64Reg)0xFF, bool warn_64bit_offset = true) const;
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void WriteFloatModRM(XEmitter *emit, FloatOp op);
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void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits);
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// This one is public - must be written to
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u64 offset; // use RIP-relative as much as possible - 64-bit immediates are not available.
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@ -247,6 +254,7 @@ private:
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void WriteSSEOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(int size, u8 sseOp, bool packed, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteFloatLoadStore(int bits, FloatOp op, OpArg arg);
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void WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg &a1, const OpArg &a2);
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protected:
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@ -427,6 +435,28 @@ public:
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void REP();
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void REPNE();
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// x87
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enum x87StatusWordBits {
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x87_InvalidOperation = 0x1,
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x87_DenormalizedOperand = 0x2,
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x87_DivisionByZero = 0x4,
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x87_Overflow = 0x8,
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x87_Underflow = 0x10,
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x87_Precision = 0x20,
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x87_StackFault = 0x40,
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x87_ErrorSummary = 0x80,
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x87_C0 = 0x100,
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x87_C1 = 0x200,
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x87_C2 = 0x400,
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x87_TopOfStack = 0x2000 | 0x1000 | 0x800,
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x87_C3 = 0x4000,
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x87_FPUBusy = 0x8000,
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};
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void FLD(int bits, OpArg src);
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void FST(int bits, OpArg dest);
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void FSTP(int bits, OpArg dest);
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void FNSTSW_AX();
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void FWAIT();
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// SSE/SSE2: Floating point arithmetic
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@ -553,6 +583,7 @@ public:
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void PUNPCKLWD(X64Reg dest, const OpArg &arg);
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void PUNPCKLDQ(X64Reg dest, const OpArg &arg);
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void PTEST(X64Reg dest, OpArg arg);
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void PAND(X64Reg dest, OpArg arg);
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void PANDN(X64Reg dest, OpArg arg);
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void PXOR(X64Reg dest, OpArg arg);
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@ -608,6 +639,7 @@ public:
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void PSRLW(X64Reg reg, int shift);
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void PSRLD(X64Reg reg, int shift);
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void PSRLQ(X64Reg reg, int shift);
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void PSRLQ(X64Reg reg, OpArg arg);
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void PSLLW(X64Reg reg, int shift);
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void PSLLD(X64Reg reg, int shift);
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@ -622,6 +654,8 @@ public:
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void VMULSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void VDIVSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void VSQRTSD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void RTDSC();
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@ -15,11 +15,11 @@ static const unsigned short FPU_ROUND_MASK = 3 << 10;
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#endif
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// OR-mask for disabling FPU exceptions (bits 7-12 in the MXCSR register)
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const u32 EXCEPTION_MASK = 0x1F80;
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static const u32 EXCEPTION_MASK = 0x1F80;
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// Denormals-Are-Zero (non-IEEE mode: denormal inputs are set to +/- 0)
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const u32 DAZ = 0x40;
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static const u32 DAZ = 0x40;
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// Flush-To-Zero (non-IEEE mode: denormal outputs are set to +/- 0)
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const u32 FTZ = 0x8000;
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static const u32 FTZ = 0x8000;
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namespace FPURoundMode
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{
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@ -100,8 +100,7 @@ namespace FPURoundMode
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FTZ, // flush-to-zero only
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FTZ | DAZ, // flush-to-zero and denormals-are-zero (may not be supported)
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};
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// FIXME: proper (?) non-IEEE mode emulation causes issues in lots of games
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if (nonIEEEMode && false)
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if (nonIEEEMode)
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{
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csr |= denormalLUT[cpu_info.bFlushToZero];
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}
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@ -231,3 +231,38 @@ inline u32 ConvertToSingleFTZ(u64 x)
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return (x >> 32) & 0x80000000;
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}
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}
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inline u64 ConvertToDouble(u32 _x)
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{
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// This is a little-endian re-implementation of the algorithm described in
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// the PowerPC Programming Environments Manual for loading single
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// precision floating point numbers.
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// See page 566 of http://www.freescale.com/files/product/doc/MPCFPE32B.pdf
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u64 x = _x;
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u64 exp = (x >> 23) & 0xff;
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u64 frac = x & 0x007fffff;
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if (exp > 0 && exp < 255) // Normal number
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{
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u64 y = !(exp >> 7);
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u64 z = y << 61 | y << 60 | y << 59;
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return ((x & 0xc0000000) << 32) | z | ((x & 0x3fffffff) << 29);
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}
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else if (exp == 0 && frac != 0) // Subnormal number
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{
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exp = 1023 - 126;
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do
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{
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frac <<= 1;
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exp -= 1;
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} while ((frac & 0x00800000) == 0);
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return ((x & 0x80000000) << 32) | (exp << 52) | ((frac & 0x007fffff) << 29);
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}
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else // QNaN, SNaN or Zero
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{
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u64 y = exp >> 7;
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u64 z = y << 61 | y << 60 | y << 59;
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return ((x & 0xc0000000) << 32) | z | ((x & 0x3fffffff) << 29);
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}
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}
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@ -92,9 +92,9 @@ void Interpreter::lfs(UGeckoInstruction _inst)
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u32 uTemp = Memory::Read_U32(Helper_Get_EA(_inst));
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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{
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double value = *(float*)&uTemp;
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rPS0(_inst.FD) = value;
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rPS1(_inst.FD) = value;
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u64 value = ConvertToDouble(uTemp);
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riPS0(_inst.FD) = value;
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riPS1(_inst.FD) = value;
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}
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}
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@ -104,9 +104,9 @@ void Interpreter::lfsu(UGeckoInstruction _inst)
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u32 uTemp = Memory::Read_U32(uAddress);
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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{
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double value = *(float*)&uTemp;
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rPS0(_inst.FD) = value;
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rPS1(_inst.FD) = value;
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u64 value = ConvertToDouble(uTemp);
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riPS0(_inst.FD) = value;
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riPS1(_inst.FD) = value;
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m_GPR[_inst.RA] = uAddress;
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}
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@ -118,9 +118,9 @@ void Interpreter::lfsux(UGeckoInstruction _inst)
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u32 uTemp = Memory::Read_U32(uAddress);
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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{
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double value = *(float*)&uTemp;
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rPS0(_inst.FD) = value;
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rPS1(_inst.FD) = value;
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u64 value = ConvertToDouble(uTemp);
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riPS0(_inst.FD) = value;
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riPS1(_inst.FD) = value;
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m_GPR[_inst.RA] = uAddress;
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}
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}
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@ -130,9 +130,9 @@ void Interpreter::lfsx(UGeckoInstruction _inst)
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u32 uTemp = Memory::Read_U32(Helper_Get_EA_X(_inst));
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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{
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double value = *(float*)&uTemp;
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rPS0(_inst.FD) = value;
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rPS1(_inst.FD) = value;
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u64 value = ConvertToDouble(uTemp);
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riPS0(_inst.FD) = value;
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riPS1(_inst.FD) = value;
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}
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}
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@ -281,9 +281,6 @@ void Interpreter::stfdu(UGeckoInstruction _inst)
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void Interpreter::stfs(UGeckoInstruction _inst)
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{
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//double value = rPS0(_inst.FS);
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//float fTemp = (float)value;
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//Memory::Write_U32(*(u32*)&fTemp, Helper_Get_EA(_inst));
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Memory::Write_U32(ConvertToSingle(riPS0(_inst.FS)), Helper_Get_EA(_inst));
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}
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@ -374,7 +374,7 @@ void RegCache::Flush(FlushMode mode)
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{
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if (locks[i])
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{
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PanicAlert("Someone forgot to unlock PPC reg %i.", i);
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PanicAlert("Someone forgot to unlock PPC reg %i (X64 reg %i).", i, RX(i));
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}
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if (regs[i].away)
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{
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@ -12,6 +12,8 @@
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#include "Core/PowerPC/Jit64/JitAsm.h"
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#include "Core/PowerPC/Jit64/JitRegCache.h"
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namespace {
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// pshufb todo: MOVQ
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const u8 GC_ALIGNED16(bswapShuffle1x4[16]) = {3, 2, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
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const u8 GC_ALIGNED16(bswapShuffle2x4[16]) = {3, 2, 1, 0, 7, 6, 5, 4, 8, 9, 10, 11, 12, 13, 14, 15};
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@ -19,11 +21,10 @@ const u8 GC_ALIGNED16(bswapShuffle1x8[16]) = {7, 6, 5, 4, 3, 2, 1, 0, 8, 9, 10,
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const u8 GC_ALIGNED16(bswapShuffle1x8Dupe[16]) = {7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0};
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const u8 GC_ALIGNED16(bswapShuffle2x8[16]) = {7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8};
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namespace {
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u64 GC_ALIGNED16(temp64);
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u32 GC_ALIGNED16(temp32);
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}
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// TODO: Add peephole optimizations for multiple consecutive lfd/lfs/stfd/stfs since they are so common,
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// and pshufb could help a lot.
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// Also add hacks for things like lfs/stfs the same reg consecutively, that is, simple memory moves.
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@ -46,11 +47,9 @@ void Jit64::lfs(UGeckoInstruction inst)
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MEMCHECK_START
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MOV(32, M(&temp32), R(EAX));
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fpr.Lock(d);
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fpr.BindToRegister(d, false);
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CVTSS2SD(fpr.RX(d), M(&temp32));
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MOVDDUP(fpr.RX(d), fpr.R(d));
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ConvertSingleToDouble(fpr.RX(d), EAX, true);
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MEMCHECK_END
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@ -226,13 +225,15 @@ void Jit64::stfs(UGeckoInstruction inst)
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return;
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}
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fpr.BindToRegister(s, true, false);
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ConvertDoubleToSingle(XMM0, fpr.RX(s));
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if (gpr.R(a).IsImm())
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{
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u32 addr = (u32)(gpr.R(a).offset + offset);
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if (Memory::IsRAMAddress(addr))
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{
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if (cpu_info.bSSSE3) {
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CVTSD2SS(XMM0, fpr.R(s));
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PSHUFB(XMM0, M((void *)bswapShuffle1x4));
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WriteFloatToConstRamAddress(XMM0, addr);
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return;
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@ -241,7 +242,6 @@ void Jit64::stfs(UGeckoInstruction inst)
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else if (addr == 0xCC008000)
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{
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// Float directly to write gather pipe! Fun!
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CVTSD2SS(XMM0, fpr.R(s));
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CALL((void*)asm_routines.fifoDirectWriteFloat);
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// TODO
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js.fifoBytesThisBlock += 4;
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@ -251,7 +251,6 @@ void Jit64::stfs(UGeckoInstruction inst)
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gpr.FlushLockX(ABI_PARAM1, ABI_PARAM2);
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gpr.Lock(a);
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fpr.Lock(s);
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MOV(32, R(ABI_PARAM2), gpr.R(a));
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ADD(32, R(ABI_PARAM2), Imm32(offset));
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if (update && offset)
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@ -266,7 +265,6 @@ void Jit64::stfs(UGeckoInstruction inst)
|
||||
|
||||
MEMCHECK_END
|
||||
}
|
||||
CVTSD2SS(XMM0, fpr.R(s));
|
||||
SafeWriteFloatToReg(XMM0, ABI_PARAM2, RegistersInUse());
|
||||
gpr.UnlockAll();
|
||||
gpr.UnlockAllX();
|
||||
@ -281,11 +279,14 @@ void Jit64::stfsx(UGeckoInstruction inst)
|
||||
|
||||
// We can take a shortcut here - it's not likely that a hardware access would use this instruction.
|
||||
gpr.FlushLockX(ABI_PARAM1);
|
||||
fpr.Lock(inst.RS);
|
||||
MOV(32, R(ABI_PARAM1), gpr.R(inst.RB));
|
||||
if (inst.RA)
|
||||
ADD(32, R(ABI_PARAM1), gpr.R(inst.RA));
|
||||
CVTSD2SS(XMM0, fpr.R(inst.RS));
|
||||
|
||||
int s = inst.RS;
|
||||
fpr.Lock(s);
|
||||
fpr.BindToRegister(s, true, false);
|
||||
ConvertDoubleToSingle(XMM0, fpr.RX(s));
|
||||
MOVD_xmm(R(EAX), XMM0);
|
||||
SafeWriteRegToReg(EAX, ABI_PARAM1, 32, 0, RegistersInUse());
|
||||
|
||||
@ -304,21 +305,20 @@ void Jit64::lfsx(UGeckoInstruction inst)
|
||||
{
|
||||
ADD(32, R(EAX), gpr.R(inst.RA));
|
||||
}
|
||||
if (cpu_info.bSSSE3 && !js.memcheck) {
|
||||
fpr.Lock(inst.RS);
|
||||
fpr.BindToRegister(inst.RS, false, true);
|
||||
X64Reg r = fpr.R(inst.RS).GetSimpleReg();
|
||||
fpr.BindToRegister(inst.RS, false);
|
||||
X64Reg s = fpr.RX(inst.RS);
|
||||
if (cpu_info.bSSSE3 && !js.memcheck) {
|
||||
#ifdef _M_IX86
|
||||
AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
|
||||
MOVD_xmm(r, MDisp(EAX, (u32)Memory::base));
|
||||
MOVD_xmm(XMM0, MDisp(EAX, (u32)Memory::base));
|
||||
#else
|
||||
MOVD_xmm(r, MComplex(RBX, EAX, SCALE_1, 0));
|
||||
MOVD_xmm(XMM0, MComplex(RBX, EAX, SCALE_1, 0));
|
||||
#endif
|
||||
MEMCHECK_START
|
||||
|
||||
PSHUFB(r, M((void *)bswapShuffle1x4));
|
||||
CVTSS2SD(r, R(r));
|
||||
MOVDDUP(r, R(r));
|
||||
PSHUFB(XMM0, M((void *)bswapShuffle1x4));
|
||||
ConvertSingleToDouble(s, XMM0);
|
||||
|
||||
MEMCHECK_END
|
||||
} else {
|
||||
@ -326,11 +326,7 @@ void Jit64::lfsx(UGeckoInstruction inst)
|
||||
|
||||
MEMCHECK_START
|
||||
|
||||
MOV(32, M(&temp32), R(EAX));
|
||||
CVTSS2SD(XMM0, M(&temp32));
|
||||
fpr.Lock(inst.RS);
|
||||
fpr.BindToRegister(inst.RS, false, true);
|
||||
MOVDDUP(fpr.R(inst.RS).GetSimpleReg(), R(XMM0));
|
||||
ConvertSingleToDouble(s, EAX, true);
|
||||
|
||||
MEMCHECK_END
|
||||
}
|
||||
|
||||
@ -1290,10 +1290,12 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
|
||||
}
|
||||
case DupSingleToMReg: {
|
||||
if (!thisUsed) break;
|
||||
X64Reg reg = fregURegWithoutMov(RI, I);
|
||||
Jit->CVTSS2SD(reg, fregLocForInst(RI, getOp1(I)));
|
||||
Jit->MOVDDUP(reg, R(reg));
|
||||
RI.fregs[reg] = I;
|
||||
|
||||
X64Reg input = fregEnsureInReg(RI, getOp1(I));
|
||||
X64Reg output = fregURegWithoutMov(RI, I);
|
||||
Jit->ConvertSingleToDouble(output, input);
|
||||
|
||||
RI.fregs[output] = I;
|
||||
fregNormalRegClear(RI, I);
|
||||
break;
|
||||
}
|
||||
@ -1414,9 +1416,12 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
|
||||
}
|
||||
case DoubleToSingle: {
|
||||
if (!thisUsed) break;
|
||||
X64Reg reg = fregURegWithoutMov(RI, I);
|
||||
Jit->CVTSD2SS(reg, fregLocForInst(RI, getOp1(I)));
|
||||
RI.fregs[reg] = I;
|
||||
|
||||
X64Reg input = fregEnsureInReg(RI, getOp1(I));
|
||||
X64Reg output = fregURegWithoutMov(RI, I);
|
||||
Jit->ConvertDoubleToSingle(output, input);
|
||||
|
||||
RI.fregs[output] = I;
|
||||
fregNormalRegClear(RI, I);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -416,6 +416,200 @@ void EmuCodeBlock::ForceSinglePrecisionP(X64Reg xmm) {
|
||||
}
|
||||
}
|
||||
|
||||
static u32 GC_ALIGNED16(temp32);
|
||||
static u64 GC_ALIGNED16(temp64);
|
||||
#ifdef _WIN32
|
||||
#include <intrin.h>
|
||||
#ifdef _M_X64
|
||||
static const __m128i GC_ALIGNED16(single_qnan_bit) = _mm_set_epi64x(0, 0x0000000000400000);
|
||||
static const __m128i GC_ALIGNED16(single_exponent) = _mm_set_epi64x(0, 0x000000007f800000);
|
||||
static const __m128i GC_ALIGNED16(double_qnan_bit) = _mm_set_epi64x(0, 0x0008000000000000);
|
||||
static const __m128i GC_ALIGNED16(double_exponent) = _mm_set_epi64x(0, 0x7ff0000000000000);
|
||||
#else
|
||||
static const __m128i GC_ALIGNED16(single_qnan_bit) = _mm_set_epi32(0, 0, 0x00000000, 0x00400000);
|
||||
static const __m128i GC_ALIGNED16(single_exponent) = _mm_set_epi32(0, 0, 0x00000000, 0x7f800000);
|
||||
static const __m128i GC_ALIGNED16(double_qnan_bit) = _mm_set_epi32(0, 0, 0x00080000, 0x00000000);
|
||||
static const __m128i GC_ALIGNED16(double_exponent) = _mm_set_epi32(0, 0, 0x7ff00000, 0x00000000);
|
||||
#endif
|
||||
#else
|
||||
static const __uint128_t GC_ALIGNED16(single_qnan_bit) = 0x0000000000400000;
|
||||
static const __uint128_t GC_ALIGNED16(single_exponent) = 0x000000007f800000;
|
||||
static const __uint128_t GC_ALIGNED16(double_qnan_bit) = 0x0008000000000000;
|
||||
static const __uint128_t GC_ALIGNED16(double_exponent) = 0x7ff0000000000000;
|
||||
#endif
|
||||
|
||||
// Since the following float conversion functions are used in non-arithmetic PPC float instructions,
|
||||
// they must convert floats bitexact and never flush denormals to zero or turn SNaNs into QNaNs.
|
||||
// This means we can't use CVTSS2SD/CVTSD2SS :(
|
||||
// The x87 FPU doesn't even support flush-to-zero so we can use FLD+FSTP even on denormals.
|
||||
// If the number is a NaN, make sure to set the QNaN bit back to its original value.
|
||||
|
||||
// Another problem is that officially, converting doubles to single format results in undefined behavior.
|
||||
// Relying on undefined behavior is a bug so no software should ever do this.
|
||||
// In case it does happen, phire's more accurate implementation of ConvertDoubleToSingle() is reproduced below.
|
||||
|
||||
//#define MORE_ACCURATE_DOUBLETOSINGLE
|
||||
#ifdef MORE_ACCURATE_DOUBLETOSINGLE
|
||||
|
||||
#ifdef _WIN32
|
||||
#ifdef _M_X64
|
||||
static const __m128i GC_ALIGNED16(double_fraction) = _mm_set_epi64x(0, 0x000fffffffffffff);
|
||||
static const __m128i GC_ALIGNED16(double_sign_bit) = _mm_set_epi64x(0, 0x8000000000000000);
|
||||
static const __m128i GC_ALIGNED16(double_explicit_top_bit) = _mm_set_epi64x(0, 0x0010000000000000);
|
||||
static const __m128i GC_ALIGNED16(double_top_two_bits) = _mm_set_epi64x(0, 0xc000000000000000);
|
||||
static const __m128i GC_ALIGNED16(double_bottom_bits) = _mm_set_epi64x(0, 0x07ffffffe0000000);
|
||||
#else
|
||||
static const __m128i GC_ALIGNED16(double_fraction) = _mm_set_epi32(0, 0, 0x000fffff, 0xffffffff);
|
||||
static const __m128i GC_ALIGNED16(double_sign_bit) = _mm_set_epi32(0, 0, 0x80000000, 0x00000000);
|
||||
static const __m128i GC_ALIGNED16(double_explicit_top_bit) = _mm_set_epi32(0, 0, 0x00100000, 0x00000000);
|
||||
static const __m128i GC_ALIGNED16(double_top_two_bits) = _mm_set_epi32(0, 0, 0xc0000000, 0x00000000);
|
||||
static const __m128i GC_ALIGNED16(double_bottom_bits) = _mm_set_epi32(0, 0, 0x07ffffff, 0xe0000000);
|
||||
#endif
|
||||
#else
|
||||
static const __uint128_t GC_ALIGNED16(double_fraction) = 0x000fffffffffffff;
|
||||
static const __uint128_t GC_ALIGNED16(double_sign_bit) = 0x8000000000000000;
|
||||
static const __uint128_t GC_ALIGNED16(double_explicit_top_bit) = 0x0010000000000000;
|
||||
static const __uint128_t GC_ALIGNED16(double_top_two_bits) = 0xc000000000000000;
|
||||
static const __uint128_t GC_ALIGNED16(double_bottom_bits) = 0x07ffffffe0000000;
|
||||
#endif
|
||||
|
||||
// This is the same algorithm used in the interpreter (and actual hardware)
|
||||
// The documentation states that the conversion of a double with an outside the
|
||||
// valid range for a single (or a single denormal) is undefined.
|
||||
// But testing on actual hardware shows it always picks bits 0..1 and 5..34
|
||||
// unless the exponent is in the range of 874 to 896.
|
||||
void EmuCodeBlock::ConvertDoubleToSingle(X64Reg dst, X64Reg src)
|
||||
{
|
||||
MOVSD(XMM1, R(src));
|
||||
|
||||
// Grab Exponent
|
||||
PAND(XMM1, M((void *)&double_exponent));
|
||||
PSRLQ(XMM1, 52);
|
||||
MOVD_xmm(R(EAX), XMM1);
|
||||
|
||||
|
||||
// Check if the double is in the range of valid single subnormal
|
||||
CMP(16, R(EAX), Imm16(896));
|
||||
FixupBranch NoDenormalize = J_CC(CC_G);
|
||||
CMP(16, R(EAX), Imm16(874));
|
||||
FixupBranch NoDenormalize2 = J_CC(CC_L);
|
||||
|
||||
// Denormalise
|
||||
|
||||
// shift = (905 - Exponent) plus the 21 bit double to single shift
|
||||
MOV(16, R(EAX), Imm16(905 + 21));
|
||||
MOVD_xmm(XMM0, R(EAX));
|
||||
PSUBQ(XMM0, R(XMM1));
|
||||
|
||||
// xmm1 = fraction | 0x0010000000000000
|
||||
MOVSD(XMM1, R(src));
|
||||
PAND(XMM1, M((void *)&double_fraction));
|
||||
POR(XMM1, M((void *)&double_explicit_top_bit));
|
||||
|
||||
// fraction >> shift
|
||||
PSRLQ(XMM1, R(XMM0));
|
||||
|
||||
// OR the sign bit in.
|
||||
MOVSD(XMM0, R(src));
|
||||
PAND(XMM0, M((void *)&double_sign_bit));
|
||||
PSRLQ(XMM0, 32);
|
||||
POR(XMM1, R(XMM0));
|
||||
|
||||
FixupBranch end = J(false); // Goto end
|
||||
|
||||
SetJumpTarget(NoDenormalize);
|
||||
SetJumpTarget(NoDenormalize2);
|
||||
|
||||
// Don't Denormalize
|
||||
|
||||
// We want bits 0, 1
|
||||
MOVSD(XMM1, R(src));
|
||||
PAND(XMM1, M((void *)&double_top_two_bits));
|
||||
PSRLQ(XMM1, 32);
|
||||
|
||||
// And 5 through to 34
|
||||
MOVSD(XMM0, R(src));
|
||||
PAND(XMM0, M((void *)&double_bottom_bits));
|
||||
PSRLQ(XMM0, 29);
|
||||
|
||||
// OR them togther
|
||||
POR(XMM1, R(XMM0));
|
||||
|
||||
// End
|
||||
SetJumpTarget(end);
|
||||
MOVDDUP(dst, R(XMM1));
|
||||
}
|
||||
|
||||
#else // MORE_ACCURATE_DOUBLETOSINGLE
|
||||
|
||||
void EmuCodeBlock::ConvertDoubleToSingle(X64Reg dst, X64Reg src)
|
||||
{
|
||||
MOVSD(M(&temp64), src);
|
||||
MOVSD(XMM1, R(src));
|
||||
FLD(64, M(&temp64));
|
||||
CCFlags cond;
|
||||
if (cpu_info.bSSE4_1) {
|
||||
PTEST(XMM1, M((void *)&double_exponent));
|
||||
cond = CC_NC;
|
||||
} else {
|
||||
FNSTSW_AX();
|
||||
TEST(16, R(AX), Imm16(x87_InvalidOperation));
|
||||
cond = CC_Z;
|
||||
}
|
||||
FSTP(32, M(&temp32));
|
||||
MOVSS(XMM0, M(&temp32));
|
||||
FixupBranch dont_reset_qnan_bit = J_CC(cond);
|
||||
|
||||
PANDN(XMM1, M((void *)&double_qnan_bit));
|
||||
PSRLQ(XMM1, 29);
|
||||
if (cpu_info.bAVX) {
|
||||
VPANDN(XMM0, XMM1, R(XMM0));
|
||||
} else {
|
||||
PANDN(XMM1, R(XMM0));
|
||||
MOVSS(XMM0, R(XMM1));
|
||||
}
|
||||
|
||||
SetJumpTarget(dont_reset_qnan_bit);
|
||||
MOVDDUP(dst, R(XMM0));
|
||||
}
|
||||
#endif // MORE_ACCURATE_DOUBLETOSINGLE
|
||||
|
||||
void EmuCodeBlock::ConvertSingleToDouble(X64Reg dst, X64Reg src, bool src_is_gpr)
|
||||
{
|
||||
if (src_is_gpr) {
|
||||
MOV(32, M(&temp32), R(src));
|
||||
MOVD_xmm(XMM1, R(src));
|
||||
} else {
|
||||
MOVSS(M(&temp32), src);
|
||||
MOVSS(R(XMM1), src);
|
||||
}
|
||||
FLD(32, M(&temp32));
|
||||
CCFlags cond;
|
||||
if (cpu_info.bSSE4_1) {
|
||||
PTEST(XMM1, M((void *)&single_exponent));
|
||||
cond = CC_NC;
|
||||
} else {
|
||||
FNSTSW_AX();
|
||||
TEST(16, R(AX), Imm16(x87_InvalidOperation));
|
||||
cond = CC_Z;
|
||||
}
|
||||
FSTP(64, M(&temp64));
|
||||
MOVSD(dst, M(&temp64));
|
||||
FixupBranch dont_reset_qnan_bit = J_CC(cond);
|
||||
|
||||
PANDN(XMM1, M((void *)&single_qnan_bit));
|
||||
PSLLQ(XMM1, 29);
|
||||
if (cpu_info.bAVX) {
|
||||
VPANDN(dst, XMM1, R(dst));
|
||||
} else {
|
||||
PANDN(XMM1, R(dst));
|
||||
MOVSD(dst, R(XMM1));
|
||||
}
|
||||
|
||||
SetJumpTarget(dont_reset_qnan_bit);
|
||||
MOVDDUP(dst, R(dst));
|
||||
}
|
||||
|
||||
void EmuCodeBlock::JitClearCA()
|
||||
{
|
||||
AND(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(~XER_CA_MASK)); //XER.CA = 0
|
||||
|
||||
@ -48,6 +48,10 @@ public:
|
||||
|
||||
void ForceSinglePrecisionS(Gen::X64Reg xmm);
|
||||
void ForceSinglePrecisionP(Gen::X64Reg xmm);
|
||||
|
||||
// AX might get trashed
|
||||
void ConvertSingleToDouble(Gen::X64Reg dst, Gen::X64Reg src, bool src_is_gpr = false);
|
||||
void ConvertDoubleToSingle(Gen::X64Reg dst, Gen::X64Reg src);
|
||||
protected:
|
||||
std::unordered_map<u8 *, u32> registersInUseAtLoc;
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user