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[AArch64] Fix a bug in the register caches.

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This is a bug that crops if BindToRegister() is called multiple times in a row without a R() function call between them.
How to reproduce the bug:
1) Have a completely filled cache with no host register remaining
2) Call BindToRegister() with different guest registers
3) Don't call R() between the BindToRegister() calls.

This issue typically wouldn't be seen for a couple of reasons. Typically we have /plenty/ of registers in the cache, and in most cases we only call
BindToRegister() once per instruction. In the off chance that it is called multiple times, it wouldn't update the last used counts and would flush the
same register as the previous call to it.
This commit is contained in:
Ryan Houdek 2015-08-28 14:36:14 -05:00
parent a6bd2fea28
commit 2c3fa8da28
1 changed files with 5 additions and 0 deletions
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5
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
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@ -206,6 +206,8 @@ void Arm64GPRCache::BindToRegister(u32 preg, bool do_load)
{
OpArg& reg = m_guest_registers[preg];
reg.ResetLastUsed();
reg.SetDirty(true);
if (reg.GetType() == REG_NOTLOADED)
{
@ -331,6 +333,9 @@ void Arm64FPRCache::BindToRegister(u32 preg, bool do_load, bool only_lower)
OpArg& reg = m_guest_registers[preg];
bool was_dirty = reg.IsDirty();
reg.ResetLastUsed();
reg.SetDirty(true);
switch (reg.GetType())
{