diff --git a/Source/Core/Core/Src/Core.cpp b/Source/Core/Core/Src/Core.cpp
index 010946b84e..4dd364599b 100644
--- a/Source/Core/Core/Src/Core.cpp
+++ b/Source/Core/Core/Src/Core.cpp
@@ -300,9 +300,7 @@ THREAD_RETURN CpuThread(void *pArg)
 	{
 		#ifdef _M_X64
 			// Let's run under memory watch
-			#ifndef JITTEST
 			EMM::InstallExceptionHandler();
-			#endif
 		#else
 			PanicAlert("32-bit platforms do not support fastmem yet. Report this bug.");
 		#endif
diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Branch.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Branch.cpp
index 61c3b628b8..252d224837 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Branch.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Branch.cpp
@@ -84,7 +84,7 @@ static IREmitter::InstLoc TestBranch(IREmitter::IRBuilder& ibuild, UGeckoInstruc
 		IREmitter::InstLoc CRCmp = ibuild.EmitIntConst(8 >> (inst.BI & 3));
 		CRTest = ibuild.EmitAnd(CRReg, CRCmp);
 		if (!(inst.BO & 8))
-			CRTest = ibuild.EmitXor(CRTest, CRCmp);
+			CRTest = ibuild.EmitXor(CRCmp, CRTest);
 	}
 
 	if ((inst.BO & 4) == 0) {
diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp
index ae7ecec9ce..e21feef070 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp
@@ -146,6 +146,13 @@ void Jit64::xorx(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(Integer)
+	if (inst.RB == inst.RS)
+	{
+		IREmitter::InstLoc val = ibuild.EmitStoreGReg(ibuild.EmitIntConst(0), inst.RA);
+		if (inst.Rc)
+			ComputeRC(ibuild, val);
+		return;
+	}
 	IREmitter::InstLoc val = ibuild.EmitLoadGReg(inst.RB);
 	val = ibuild.EmitXor(ibuild.EmitLoadGReg(inst.RS), val);
 	ibuild.EmitStoreGReg(val, inst.RA);
diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_LoadStore.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_LoadStore.cpp
index 4e0132cac6..d8b721c5c1 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_LoadStore.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_LoadStore.cpp
@@ -61,7 +61,7 @@ void Jit64::lXz(UGeckoInstruction inst)
 	{
 	case 32: val = ibuild.EmitLoad32(addr); break; //lwz	
 	case 40: val = ibuild.EmitLoad16(addr); break; //lhz
-	case 34: val = ibuild.EmitLoad8(addr);  break; //lbz
+	case 34: val = ibuild.EmitLoad8(addr);  break; //lbz - lbzu crashes GFZP01 @ 0x8008575C
 	default: PanicAlert("lXz: invalid access size");
 	}
 	ibuild.EmitStoreGReg(val, inst.RD);
@@ -164,7 +164,7 @@ void Jit64::stXx(UGeckoInstruction inst)
 	}
 }
 
-// A few games use these heavily in video codecs.
+// A few games use these heavily in video codecs. (GFZP01 @ 0x80020E18)
 void Jit64::lmw(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_SystemRegisters.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_SystemRegisters.cpp
index 95d4c20e7e..053c29a3b3 100644
--- a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_SystemRegisters.cpp
+++ b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_SystemRegisters.cpp
@@ -37,6 +37,10 @@ void Jit64::mtspr(UGeckoInstruction inst)
 		JITDISABLE(SystemRegisters)
 		u32 iIndex = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
 	switch(iIndex) {
+		case SPR_TL:
+		case SPR_TU:
+			Default(inst);
+			return;
 		case SPR_LR:
 			ibuild.EmitStoreLink(ibuild.EmitLoadGReg(inst.RD));
 			return;
@@ -70,6 +74,10 @@ void Jit64::mfspr(UGeckoInstruction inst)
 		u32 iIndex = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
 	switch (iIndex)
 	{
+	case SPR_TL:
+	case SPR_TU:
+		Default(inst);
+		return;
 	case SPR_LR:
 		ibuild.EmitStoreGReg(ibuild.EmitLoadLink(), inst.RD);
 		return;
diff --git a/Source/Core/Core/Src/PowerPC/JitCommon/Jit_Tables.cpp b/Source/Core/Core/Src/PowerPC/JitCommon/Jit_Tables.cpp
index d5fa033081..f87da3b1ef 100644
--- a/Source/Core/Core/Src/PowerPC/JitCommon/Jit_Tables.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitCommon/Jit_Tables.cpp
@@ -82,7 +82,7 @@ static GekkoOPTemplate primarytable[] =
 	{32, &Jit64::lXz}, //"lwz",  OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
 	{33, &Jit64::lXz}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
 	{34, &Jit64::lXz}, //"lbz",  OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
-	{35, &Jit64::lXz}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
+	{35, &Jit64::Default}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
 	{40, &Jit64::lXz}, //"lhz",  OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
 	{41, &Jit64::lXz}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
 #else