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105 lines
4.1 KiB
C
105 lines
4.1 KiB
C
/**
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* \file
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*
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* \brief SAMV71 clock configuration.
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*
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* Copyright (c) 2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef CONF_CLOCK_H_INCLUDED
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#define CONF_CLOCK_H_INCLUDED
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// ===== System Clock (MCK) Source Options
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS
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#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
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//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK
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// ===== Processor Clock (HCLK) Prescaler Options (Fhclk = Fsys / (SYSCLK_PRES))
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#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2
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//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4
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//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8
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//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16
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//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32
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//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64
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//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3
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// ===== System Clock (MCK) Division Options (Fmck = Fhclk / (SYSCLK_DIV))
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#define CONFIG_SYSCLK_DIV 2
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// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
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// Use mul and div effective values here.
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#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
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#define CONFIG_PLL0_MUL 25
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#define CONFIG_PLL0_DIV 1
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// ===== UPLL (UTMI) Hardware fixed at 480 MHz.
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// ===== USB Clock Source Options (Fusb = FpllX / USB_div)
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// Use div effective value here.
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//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
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#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL
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#define CONFIG_USBCLK_DIV 1
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// ===== Target frequency (Processor clock)
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// - XTAL frequency: 12MHz
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// - System clock source: PLLA
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// - System clock prescaler: 1 (divided by 1)
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// - System clock divider: 2 (divided by 2)
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// - PLLA source: XTAL
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// - PLLA output: XTAL * 25 / 1
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// - Processor clock: 12 * 25 / 1 / 1 = 300MHz
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// - System clock: 300 / 2 = 150MHz
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// ===== Target frequency (USB Clock)
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// - USB clock source: UPLL
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// - USB clock divider: 1 (not divided)
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// - UPLL frequency: 480MHz
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// - USB clock: 480 / 1 = 480MHz
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#endif /* CONF_CLOCK_H_INCLUDED */
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