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1461 lines
38 KiB
C
1461 lines
38 KiB
C
/**
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* \file
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*
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* \brief Parallel Input/Output (PIO) Controller driver for SAM.
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*
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* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include "pio.h"
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#ifndef PIO_WPMR_WPKEY_PASSWD
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# define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494Fu)
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#endif
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/**
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* \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller
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*
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* \par Purpose
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*
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* The Parallel Input/Output Controller (PIO) manages up to 32 fully
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* programmable input/output lines. Each I/O line may be dedicated as a
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* general-purpose I/O or be assigned to a function of an embedded peripheral.
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* This assures effective optimization of the pins of a product.
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*
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* @{
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*/
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#ifndef FREQ_SLOW_CLOCK_EXT
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/* External slow clock frequency (hz) */
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#define FREQ_SLOW_CLOCK_EXT 32768
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#endif
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/**
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* \brief Configure PIO internal pull-up.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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* \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be
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* configured.
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*/
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void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,
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const uint32_t ul_pull_up_enable)
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{
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/* Enable the pull-up(s) if necessary */
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if (ul_pull_up_enable) {
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p_pio->PIO_PUER = ul_mask;
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} else {
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p_pio->PIO_PUDR = ul_mask;
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}
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}
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/**
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* \brief Configure Glitch or Debouncing filter for the specified input(s).
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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* \param ul_cut_off Cuts off frequency for debouncing filter.
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*/
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void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,
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const uint32_t ul_cut_off)
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{
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#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
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/* Set Debouncing, 0 bit field no effect */
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p_pio->PIO_IFSCER = ul_mask;
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#elif (SAM3XA || SAM3U)
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/* Set Debouncing, 0 bit field no effect */
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p_pio->PIO_DIFSR = ul_mask;
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#else
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#error "Unsupported device"
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#endif
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/*
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* The debouncing filter can filter a pulse of less than 1/2 Period of a
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* programmable Divided Slow Clock:
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* Tdiv_slclk = ((DIV+1)*2).Tslow_clock
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*/
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p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT /
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(2 * (ul_cut_off))) - 1);
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}
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/**
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* \brief Set a high output level on all the PIOs defined in ul_mask.
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* This has no immediate effects on PIOs that are not output, but the PIO
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* controller will save the value if they are changed to outputs.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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*/
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void pio_set(Pio *p_pio, const uint32_t ul_mask)
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{
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p_pio->PIO_SODR = ul_mask;
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}
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/**
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* \brief Set a low output level on all the PIOs defined in ul_mask.
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* This has no immediate effects on PIOs that are not output, but the PIO
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* controller will save the value if they are changed to outputs.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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*/
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void pio_clear(Pio *p_pio, const uint32_t ul_mask)
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{
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p_pio->PIO_CODR = ul_mask;
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}
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/**
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* \brief Return 1 if one or more PIOs of the given Pin instance currently have
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* a high level; otherwise returns 0. This method returns the actual value that
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* is being read on the pin. To return the supposed output value of a pin, use
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* pio_get_output_data_status() instead.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_type PIO type.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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*
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* \retval 1 at least one PIO currently has a high level.
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* \retval 0 all PIOs have a low level.
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*/
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uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,
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const uint32_t ul_mask)
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{
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uint32_t ul_reg;
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if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) {
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ul_reg = p_pio->PIO_ODSR;
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} else {
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ul_reg = p_pio->PIO_PDSR;
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}
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if ((ul_reg & ul_mask) == 0) {
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return 0;
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} else {
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return 1;
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}
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}
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/**
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* \brief Configure IO of a PIO controller as being controlled by a specific
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* peripheral.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_type PIO type.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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*/
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void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,
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const uint32_t ul_mask)
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{
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uint32_t ul_sr;
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/* Disable interrupts on the pin(s) */
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p_pio->PIO_IDR = ul_mask;
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#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
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switch (ul_type) {
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case PIO_PERIPH_A:
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ul_sr = p_pio->PIO_ABCDSR[0];
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p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);
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ul_sr = p_pio->PIO_ABCDSR[1];
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p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);
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break;
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case PIO_PERIPH_B:
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ul_sr = p_pio->PIO_ABCDSR[0];
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p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);
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ul_sr = p_pio->PIO_ABCDSR[1];
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p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);
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break;
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#if (!SAMG)
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case PIO_PERIPH_C:
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ul_sr = p_pio->PIO_ABCDSR[0];
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p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);
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ul_sr = p_pio->PIO_ABCDSR[1];
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p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);
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break;
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case PIO_PERIPH_D:
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ul_sr = p_pio->PIO_ABCDSR[0];
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p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);
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ul_sr = p_pio->PIO_ABCDSR[1];
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p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);
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break;
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#endif
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/* Other types are invalid in this function */
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case PIO_INPUT:
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case PIO_OUTPUT_0:
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case PIO_OUTPUT_1:
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case PIO_NOT_A_PIN:
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return;
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}
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#elif (SAM3XA|| SAM3U)
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switch (ul_type) {
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case PIO_PERIPH_A:
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ul_sr = p_pio->PIO_ABSR;
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p_pio->PIO_ABSR &= (~ul_mask & ul_sr);
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break;
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case PIO_PERIPH_B:
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ul_sr = p_pio->PIO_ABSR;
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p_pio->PIO_ABSR = (ul_mask | ul_sr);
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break;
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// other types are invalid in this function
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case PIO_INPUT:
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case PIO_OUTPUT_0:
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case PIO_OUTPUT_1:
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case PIO_NOT_A_PIN:
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return;
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}
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#else
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#error "Unsupported device"
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#endif
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/* Remove the pins from under the control of PIO */
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p_pio->PIO_PDR = ul_mask;
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}
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/**
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* \brief Configure one or more pin(s) or a PIO controller as inputs.
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* Optionally, the corresponding internal pull-up(s) and glitch filter(s) can
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* be enabled.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask indicating which pin(s) to configure as input(s).
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* \param ul_attribute PIO attribute(s).
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*/
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void pio_set_input(Pio *p_pio, const uint32_t ul_mask,
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const uint32_t ul_attribute)
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{
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pio_disable_interrupt(p_pio, ul_mask);
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pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP);
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/* Enable Input Filter if necessary */
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if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) {
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p_pio->PIO_IFER = ul_mask;
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} else {
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p_pio->PIO_IFDR = ul_mask;
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}
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#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
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/* Enable de-glitch or de-bounce if necessary */
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if (ul_attribute & PIO_DEGLITCH) {
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p_pio->PIO_IFSCDR = ul_mask;
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} else {
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if (ul_attribute & PIO_DEBOUNCE) {
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p_pio->PIO_IFSCER = ul_mask;
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}
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}
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#elif (SAM3XA|| SAM3U)
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/* Enable de-glitch or de-bounce if necessary */
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if (ul_attribute & PIO_DEGLITCH) {
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p_pio->PIO_SCIFSR = ul_mask;
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} else {
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if (ul_attribute & PIO_DEBOUNCE) {
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p_pio->PIO_DIFSR = ul_mask;
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}
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}
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#else
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#error "Unsupported device"
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#endif
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/* Configure pin as input */
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p_pio->PIO_ODR = ul_mask;
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p_pio->PIO_PER = ul_mask;
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}
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/**
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* \brief Configure one or more pin(s) of a PIO controller as outputs, with
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* the given default value. Optionally, the multi-drive feature can be enabled
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* on the pin(s).
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask indicating which pin(s) to configure.
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* \param ul_default_level Default level on the pin(s).
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* \param ul_multidrive_enable Indicates if the pin(s) shall be configured as
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* open-drain.
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* \param ul_pull_up_enable Indicates if the pin shall have its pull-up
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* activated.
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*/
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void pio_set_output(Pio *p_pio, const uint32_t ul_mask,
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const uint32_t ul_default_level,
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const uint32_t ul_multidrive_enable,
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const uint32_t ul_pull_up_enable)
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{
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pio_disable_interrupt(p_pio, ul_mask);
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pio_pull_up(p_pio, ul_mask, ul_pull_up_enable);
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/* Enable multi-drive if necessary */
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if (ul_multidrive_enable) {
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p_pio->PIO_MDER = ul_mask;
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} else {
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p_pio->PIO_MDDR = ul_mask;
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}
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/* Set default value */
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if (ul_default_level) {
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p_pio->PIO_SODR = ul_mask;
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} else {
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p_pio->PIO_CODR = ul_mask;
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}
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/* Configure pin(s) as output(s) */
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p_pio->PIO_OER = ul_mask;
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p_pio->PIO_PER = ul_mask;
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}
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/**
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* \brief Perform complete pin(s) configuration; general attributes and PIO init
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* if necessary.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_type PIO type.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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* \param ul_attribute Pins attributes.
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*
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* \return Whether the pin(s) have been configured properly.
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*/
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uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,
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const uint32_t ul_mask, const uint32_t ul_attribute)
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{
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/* Configure pins */
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switch (ul_type) {
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case PIO_PERIPH_A:
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case PIO_PERIPH_B:
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#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
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case PIO_PERIPH_C:
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case PIO_PERIPH_D:
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#endif
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pio_set_peripheral(p_pio, ul_type, ul_mask);
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pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP));
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break;
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case PIO_INPUT:
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pio_set_input(p_pio, ul_mask, ul_attribute);
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break;
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case PIO_OUTPUT_0:
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case PIO_OUTPUT_1:
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pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1),
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(ul_attribute & PIO_OPENDRAIN) ? 1 : 0,
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(ul_attribute & PIO_PULLUP) ? 1 : 0);
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break;
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default:
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return 0;
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}
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return 1;
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}
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/**
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* \brief Return 1 if one or more PIOs of the given Pin are configured to
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* output a high level (even if they are not output).
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* To get the actual value of the pin, use PIO_Get() instead.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask of one or more pin(s).
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*
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* \retval 1 At least one PIO is configured to output a high level.
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* \retval 0 All PIOs are configured to output a low level.
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*/
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uint32_t pio_get_output_data_status(const Pio *p_pio,
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const uint32_t ul_mask)
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{
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if ((p_pio->PIO_ODSR & ul_mask) == 0) {
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return 0;
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} else {
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return 1;
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}
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}
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/**
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* \brief Configure PIO pin multi-driver.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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* \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be
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* configured.
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*/
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void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,
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const uint32_t ul_multi_driver_enable)
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{
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/* Enable the multi-driver if necessary */
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if (ul_multi_driver_enable) {
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p_pio->PIO_MDER = ul_mask;
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} else {
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p_pio->PIO_MDDR = ul_mask;
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}
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}
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/**
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* \brief Get multi-driver status.
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*
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* \param p_pio Pointer to a PIO instance.
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*
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* \return The multi-driver mask value.
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*/
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uint32_t pio_get_multi_driver_status(const Pio *p_pio)
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{
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return p_pio->PIO_MDSR;
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}
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#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
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/**
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* \brief Configure PIO pin internal pull-down.
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*
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* \param p_pio Pointer to a PIO instance.
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* \param ul_mask Bitmask of one or more pin(s) to configure.
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* \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall
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* be configured.
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*/
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void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,
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const uint32_t ul_pull_down_enable)
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{
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/* Enable the pull-down if necessary */
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if (ul_pull_down_enable) {
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p_pio->PIO_PPDER = ul_mask;
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} else {
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p_pio->PIO_PPDDR = ul_mask;
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}
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}
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#endif
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/**
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* \brief Enable PIO output write for synchronous data output.
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*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Bitmask of one or more pin(s) to configure.
|
|
*/
|
|
void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_OWER = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable PIO output write.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Bitmask of one or more pin(s) to configure.
|
|
*/
|
|
void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_OWDR = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Read PIO output write status.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The output write mask value.
|
|
*/
|
|
uint32_t pio_get_output_write_status(const Pio *p_pio)
|
|
{
|
|
return p_pio->PIO_OWSR;
|
|
}
|
|
|
|
/**
|
|
* \brief Synchronously write on output pins.
|
|
* \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are
|
|
* written.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Bitmask of one or more pin(s) to configure.
|
|
*/
|
|
void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_ODSR = ul_mask;
|
|
}
|
|
|
|
#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
|
|
/**
|
|
* \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is
|
|
* active.
|
|
* Disabling the Schmitt Trigger is requested when using the QTouch Library.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Bitmask of one or more pin(s) to configure.
|
|
*/
|
|
void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_SCHMITT = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Get PIO pin schmitt trigger status.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The schmitt trigger mask value.
|
|
*/
|
|
uint32_t pio_get_schmitt_trigger(const Pio *p_pio)
|
|
{
|
|
return p_pio->PIO_SCHMITT;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* \brief Configure the given interrupt source.
|
|
* Interrupt can be configured to trigger on rising edge, falling edge,
|
|
* high level, low level or simply on level change.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Interrupt source bit map.
|
|
* \param ul_attr Interrupt source attributes.
|
|
*/
|
|
void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask,
|
|
const uint32_t ul_attr)
|
|
{
|
|
/* Configure additional interrupt mode registers. */
|
|
if (ul_attr & PIO_IT_AIME) {
|
|
/* Enable additional interrupt mode. */
|
|
p_pio->PIO_AIMER = ul_mask;
|
|
|
|
/* If bit field of the selected pin is 1, set as
|
|
Rising Edge/High level detection event. */
|
|
if (ul_attr & PIO_IT_RE_OR_HL) {
|
|
/* Rising Edge or High Level */
|
|
p_pio->PIO_REHLSR = ul_mask;
|
|
} else {
|
|
/* Falling Edge or Low Level */
|
|
p_pio->PIO_FELLSR = ul_mask;
|
|
}
|
|
|
|
/* If bit field of the selected pin is 1, set as
|
|
edge detection source. */
|
|
if (ul_attr & PIO_IT_EDGE) {
|
|
/* Edge select */
|
|
p_pio->PIO_ESR = ul_mask;
|
|
} else {
|
|
/* Level select */
|
|
p_pio->PIO_LSR = ul_mask;
|
|
}
|
|
} else {
|
|
/* Disable additional interrupt mode. */
|
|
p_pio->PIO_AIMDR = ul_mask;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Enable the given interrupt source.
|
|
* The PIO must be configured as an NVIC interrupt source as well.
|
|
* The status register of the corresponding PIO controller is cleared
|
|
* prior to enabling the interrupt.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Interrupt sources bit map.
|
|
*/
|
|
void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_ISR;
|
|
p_pio->PIO_IER = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable a given interrupt source, with no added side effects.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Interrupt sources bit map.
|
|
*/
|
|
void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_IDR = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Read PIO interrupt status.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The interrupt status mask value.
|
|
*/
|
|
uint32_t pio_get_interrupt_status(const Pio *p_pio)
|
|
{
|
|
return p_pio->PIO_ISR;
|
|
}
|
|
|
|
/**
|
|
* \brief Read PIO interrupt mask.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The interrupt mask value.
|
|
*/
|
|
uint32_t pio_get_interrupt_mask(const Pio *p_pio)
|
|
{
|
|
return p_pio->PIO_IMR;
|
|
}
|
|
|
|
/**
|
|
* \brief Set additional interrupt mode.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Interrupt sources bit map.
|
|
* \param ul_attribute Pin(s) attributes.
|
|
*/
|
|
void pio_set_additional_interrupt_mode(Pio *p_pio,
|
|
const uint32_t ul_mask, const uint32_t ul_attribute)
|
|
{
|
|
/* Enables additional interrupt mode if needed */
|
|
if (ul_attribute & PIO_IT_AIME) {
|
|
/* Enables additional interrupt mode */
|
|
p_pio->PIO_AIMER = ul_mask;
|
|
|
|
/* Configures the Polarity of the event detection */
|
|
/* (Rising/Falling Edge or High/Low Level) */
|
|
if (ul_attribute & PIO_IT_RE_OR_HL) {
|
|
/* Rising Edge or High Level */
|
|
p_pio->PIO_REHLSR = ul_mask;
|
|
} else {
|
|
/* Falling Edge or Low Level */
|
|
p_pio->PIO_FELLSR = ul_mask;
|
|
}
|
|
|
|
/* Configures the type of event detection (Edge or Level) */
|
|
if (ul_attribute & PIO_IT_EDGE) {
|
|
/* Edge select */
|
|
p_pio->PIO_ESR = ul_mask;
|
|
} else {
|
|
/* Level select */
|
|
p_pio->PIO_LSR = ul_mask;
|
|
}
|
|
} else {
|
|
/* Disable additional interrupt mode */
|
|
p_pio->PIO_AIMDR = ul_mask;
|
|
}
|
|
}
|
|
|
|
#ifndef PIO_WPMR_WPKEY_PASSWD
|
|
#define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494FU)
|
|
#endif
|
|
|
|
/**
|
|
* \brief Enable or disable write protect of PIO registers.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_enable 1 to enable, 0 to disable.
|
|
*/
|
|
void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable)
|
|
{
|
|
p_pio->PIO_WPMR = PIO_WPMR_WPKEY_PASSWD | (ul_enable & PIO_WPMR_WPEN);
|
|
}
|
|
|
|
/**
|
|
* \brief Read write protect status.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return Return write protect status.
|
|
*/
|
|
uint32_t pio_get_writeprotect_status(const Pio *p_pio)
|
|
{
|
|
return p_pio->PIO_WPSR;
|
|
}
|
|
|
|
/**
|
|
* \brief Return the value of a pin.
|
|
*
|
|
* \param ul_pin The pin number.
|
|
*
|
|
* \return The pin value.
|
|
*
|
|
* \note If pin is output: a pull-up or pull-down could hide the actual value.
|
|
* The function \ref pio_get can be called to get the actual pin output
|
|
* level.
|
|
* \note If pin is input: PIOx must be clocked to sample the signal.
|
|
* See PMC driver.
|
|
*/
|
|
uint32_t pio_get_pin_value(uint32_t ul_pin)
|
|
{
|
|
Pio *p_pio = pio_get_pin_group(ul_pin);
|
|
|
|
return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1;
|
|
}
|
|
|
|
/**
|
|
* \brief Drive a GPIO pin to 1.
|
|
*
|
|
* \param ul_pin The pin index.
|
|
*
|
|
* \note The function \ref pio_configure_pin must be called beforehand.
|
|
*/
|
|
void pio_set_pin_high(uint32_t ul_pin)
|
|
{
|
|
Pio *p_pio = pio_get_pin_group(ul_pin);
|
|
|
|
/* Value to be driven on the I/O line: 1. */
|
|
p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);
|
|
}
|
|
|
|
/**
|
|
* \brief Drive a GPIO pin to 0.
|
|
*
|
|
* \param ul_pin The pin index.
|
|
*
|
|
* \note The function \ref pio_configure_pin must be called before.
|
|
*/
|
|
void pio_set_pin_low(uint32_t ul_pin)
|
|
{
|
|
Pio *p_pio = pio_get_pin_group(ul_pin);
|
|
|
|
/* Value to be driven on the I/O line: 0. */
|
|
p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);
|
|
}
|
|
|
|
/**
|
|
* \brief Toggle a GPIO pin.
|
|
*
|
|
* \param ul_pin The pin index.
|
|
*
|
|
* \note The function \ref pio_configure_pin must be called before.
|
|
*/
|
|
void pio_toggle_pin(uint32_t ul_pin)
|
|
{
|
|
Pio *p_pio = pio_get_pin_group(ul_pin);
|
|
|
|
if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) {
|
|
/* Value to be driven on the I/O line: 0. */
|
|
p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);
|
|
} else {
|
|
/* Value to be driven on the I/O line: 1. */
|
|
p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Perform complete pin(s) configuration; general attributes and PIO init
|
|
* if necessary.
|
|
*
|
|
* \param ul_pin Bitmask of one or more pin(s) to configure.
|
|
* \param ul_flags Pins attributes.
|
|
*
|
|
* \return Whether the pin(s) have been configured properly.
|
|
*/
|
|
uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags)
|
|
{
|
|
Pio *p_pio = pio_get_pin_group(ul_pin);
|
|
|
|
/* Configure pins */
|
|
switch (ul_flags & PIO_TYPE_Msk) {
|
|
case PIO_TYPE_PIO_PERIPH_A:
|
|
pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F)));
|
|
pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
|
|
(ul_flags & PIO_PULLUP));
|
|
break;
|
|
case PIO_TYPE_PIO_PERIPH_B:
|
|
pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F)));
|
|
pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
|
|
(ul_flags & PIO_PULLUP));
|
|
break;
|
|
#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
|
|
case PIO_TYPE_PIO_PERIPH_C:
|
|
pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F)));
|
|
pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
|
|
(ul_flags & PIO_PULLUP));
|
|
break;
|
|
case PIO_TYPE_PIO_PERIPH_D:
|
|
pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F)));
|
|
pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
|
|
(ul_flags & PIO_PULLUP));
|
|
break;
|
|
#endif
|
|
|
|
case PIO_TYPE_PIO_INPUT:
|
|
pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags);
|
|
break;
|
|
|
|
case PIO_TYPE_PIO_OUTPUT_0:
|
|
case PIO_TYPE_PIO_OUTPUT_1:
|
|
pio_set_output(p_pio, (1 << (ul_pin & 0x1F)),
|
|
((ul_flags & PIO_TYPE_PIO_OUTPUT_1)
|
|
== PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,
|
|
(ul_flags & PIO_OPENDRAIN) ? 1 : 0,
|
|
(ul_flags & PIO_PULLUP) ? 1 : 0);
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* \brief Drive a GPIO port to 1.
|
|
*
|
|
* \param p_pio Base address of the PIO port.
|
|
* \param ul_mask Bitmask of one or more pin(s) to toggle.
|
|
*/
|
|
void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask)
|
|
{
|
|
/* Value to be driven on the I/O line: 1. */
|
|
p_pio->PIO_SODR = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Drive a GPIO port to 0.
|
|
*
|
|
* \param p_pio Base address of the PIO port.
|
|
* \param ul_mask Bitmask of one or more pin(s) to toggle.
|
|
*/
|
|
void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask)
|
|
{
|
|
/* Value to be driven on the I/O line: 0. */
|
|
p_pio->PIO_CODR = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Toggle a GPIO group.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Bitmask of one or more pin(s) to configure.
|
|
*/
|
|
void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask)
|
|
{
|
|
if (p_pio->PIO_ODSR & ul_mask) {
|
|
/* Value to be driven on the I/O line: 0. */
|
|
p_pio->PIO_CODR = ul_mask;
|
|
} else {
|
|
/* Value to be driven on the I/O line: 1. */
|
|
p_pio->PIO_SODR = ul_mask;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Perform complete pin(s) configuration; general attributes and PIO init
|
|
* if necessary.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Bitmask of one or more pin(s) to configure.
|
|
* \param ul_flags Pin(s) attributes.
|
|
*
|
|
* \return Whether the pin(s) have been configured properly.
|
|
*/
|
|
uint32_t pio_configure_pin_group(Pio *p_pio,
|
|
uint32_t ul_mask, const uint32_t ul_flags)
|
|
{
|
|
/* Configure pins */
|
|
switch (ul_flags & PIO_TYPE_Msk) {
|
|
case PIO_TYPE_PIO_PERIPH_A:
|
|
pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask);
|
|
pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
|
|
break;
|
|
case PIO_TYPE_PIO_PERIPH_B:
|
|
pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask);
|
|
pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
|
|
break;
|
|
#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
|
|
case PIO_TYPE_PIO_PERIPH_C:
|
|
pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask);
|
|
pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
|
|
break;
|
|
case PIO_TYPE_PIO_PERIPH_D:
|
|
pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask);
|
|
pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
|
|
break;
|
|
#endif
|
|
|
|
case PIO_TYPE_PIO_INPUT:
|
|
pio_set_input(p_pio, ul_mask, ul_flags);
|
|
break;
|
|
|
|
case PIO_TYPE_PIO_OUTPUT_0:
|
|
case PIO_TYPE_PIO_OUTPUT_1:
|
|
pio_set_output(p_pio, ul_mask,
|
|
((ul_flags & PIO_TYPE_PIO_OUTPUT_1)
|
|
== PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,
|
|
(ul_flags & PIO_OPENDRAIN) ? 1 : 0,
|
|
(ul_flags & PIO_PULLUP) ? 1 : 0);
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* \brief Enable interrupt for a GPIO pin.
|
|
*
|
|
* \param ul_pin The pin index.
|
|
*
|
|
* \note The function \ref gpio_configure_pin must be called before.
|
|
*/
|
|
void pio_enable_pin_interrupt(uint32_t ul_pin)
|
|
{
|
|
Pio *p_pio = pio_get_pin_group(ul_pin);
|
|
|
|
p_pio->PIO_IER = 1 << (ul_pin & 0x1F);
|
|
}
|
|
|
|
|
|
/**
|
|
* \brief Disable interrupt for a GPIO pin.
|
|
*
|
|
* \param ul_pin The pin index.
|
|
*
|
|
* \note The function \ref gpio_configure_pin must be called before.
|
|
*/
|
|
void pio_disable_pin_interrupt(uint32_t ul_pin)
|
|
{
|
|
Pio *p_pio = pio_get_pin_group(ul_pin);
|
|
|
|
p_pio->PIO_IDR = 1 << (ul_pin & 0x1F);
|
|
}
|
|
|
|
|
|
/**
|
|
* \brief Return GPIO port for a GPIO pin.
|
|
*
|
|
* \param ul_pin The pin index.
|
|
*
|
|
* \return Pointer to \ref Pio struct for GPIO port.
|
|
*/
|
|
Pio *pio_get_pin_group(uint32_t ul_pin)
|
|
{
|
|
Pio *p_pio;
|
|
|
|
#if (SAM4C || SAM4CP)
|
|
# ifdef ID_PIOD
|
|
if (ul_pin > PIO_PC9_IDX) {
|
|
p_pio = PIOD;
|
|
} else if (ul_pin > PIO_PB31_IDX) {
|
|
# else
|
|
if (ul_pin > PIO_PB31_IDX) {
|
|
# endif
|
|
p_pio = PIOC;
|
|
} else {
|
|
p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
|
|
}
|
|
#elif (SAM4CM)
|
|
if (ul_pin > PIO_PB21_IDX) {
|
|
p_pio = PIOC;
|
|
} else {
|
|
p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
|
|
}
|
|
#else
|
|
p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
|
|
#endif
|
|
return p_pio;
|
|
}
|
|
|
|
/**
|
|
* \brief Return GPIO port peripheral ID for a GPIO pin.
|
|
*
|
|
* \param ul_pin The pin index.
|
|
*
|
|
* \return GPIO port peripheral ID.
|
|
*/
|
|
uint32_t pio_get_pin_group_id(uint32_t ul_pin)
|
|
{
|
|
uint32_t ul_id;
|
|
|
|
#if (SAM4C || SAM4CP)
|
|
# ifdef ID_PIOD
|
|
if (ul_pin > PIO_PC9_IDX) {
|
|
ul_id = ID_PIOD;
|
|
} else if (ul_pin > PIO_PB31_IDX) {
|
|
# else
|
|
if (ul_pin > PIO_PB31_IDX) {
|
|
# endif
|
|
ul_id = ID_PIOC;
|
|
} else {
|
|
ul_id = ID_PIOA + (ul_pin >> 5);
|
|
}
|
|
#elif (SAM4CM)
|
|
if (ul_pin > PIO_PB21_IDX) {
|
|
ul_id = ID_PIOC;
|
|
} else {
|
|
ul_id = ID_PIOA + (ul_pin >> 5);
|
|
}
|
|
#else
|
|
ul_id = ID_PIOA + (ul_pin >> 5);
|
|
#endif
|
|
return ul_id;
|
|
}
|
|
|
|
|
|
/**
|
|
* \brief Return GPIO port pin mask for a GPIO pin.
|
|
*
|
|
* \param ul_pin The pin index.
|
|
*
|
|
* \return GPIO port pin mask.
|
|
*/
|
|
uint32_t pio_get_pin_group_mask(uint32_t ul_pin)
|
|
{
|
|
uint32_t ul_mask = 1 << (ul_pin & 0x1F);
|
|
return ul_mask;
|
|
}
|
|
|
|
#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70)
|
|
/* Capture mode enable flag */
|
|
uint32_t pio_capture_enable_flag;
|
|
|
|
/**
|
|
* \brief Configure PIO capture mode.
|
|
* \note PIO capture mode will be disabled automatically.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mode Bitmask of one or more modes.
|
|
*/
|
|
void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode)
|
|
{
|
|
ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */
|
|
p_pio->PIO_PCMR = ul_mode;
|
|
}
|
|
|
|
/**
|
|
* \brief Enable PIO capture mode.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*/
|
|
void pio_capture_enable(Pio *p_pio)
|
|
{
|
|
p_pio->PIO_PCMR |= PIO_PCMR_PCEN;
|
|
pio_capture_enable_flag = true;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable PIO capture mode.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*/
|
|
void pio_capture_disable(Pio *p_pio)
|
|
{
|
|
p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN);
|
|
pio_capture_enable_flag = false;
|
|
}
|
|
|
|
/**
|
|
* \brief Read from Capture Reception Holding Register.
|
|
* \note Data presence should be tested before any read attempt.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param pul_data Pointer to store the data.
|
|
*
|
|
* \retval 0 Success.
|
|
* \retval 1 I/O Failure, Capture data is not ready.
|
|
*/
|
|
uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data)
|
|
{
|
|
/* Check if the data is ready */
|
|
if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) {
|
|
return 1;
|
|
}
|
|
|
|
/* Read data */
|
|
*pul_data = p_pio->PIO_PCRHR;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* \brief Enable the given interrupt source of PIO capture. The status
|
|
* register of the corresponding PIO capture controller is cleared prior
|
|
* to enabling the interrupt.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Interrupt sources bit map.
|
|
*/
|
|
void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_PCISR;
|
|
p_pio->PIO_PCIER = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable a given interrupt source of PIO capture.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Interrupt sources bit map.
|
|
*/
|
|
void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_PCIDR = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Read PIO interrupt status of PIO capture.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The interrupt status mask value.
|
|
*/
|
|
uint32_t pio_capture_get_interrupt_status(const Pio *p_pio)
|
|
{
|
|
return p_pio->PIO_PCISR;
|
|
}
|
|
|
|
/**
|
|
* \brief Read PIO interrupt mask of PIO capture.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The interrupt mask value.
|
|
*/
|
|
uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio)
|
|
{
|
|
return p_pio->PIO_PCIMR;
|
|
}
|
|
#if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
|
|
/**
|
|
* \brief Get PDC registers base address.
|
|
*
|
|
* \param p_pio Pointer to an PIO peripheral.
|
|
*
|
|
* \return PIOA PDC register base address.
|
|
*/
|
|
Pdc *pio_capture_get_pdc_base(const Pio *p_pio)
|
|
{
|
|
UNUSED(p_pio); /* Stop warning */
|
|
return PDC_PIOA;
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if (SAM4C || SAM4CP || SAM4CM || SAMG55)
|
|
/**
|
|
* \brief Set PIO IO drive.
|
|
*
|
|
* \param p_pio Pointer to an PIO peripheral.
|
|
* \param ul_line Line index (0..31).
|
|
* \param mode IO drive mode.
|
|
*/
|
|
void pio_set_io_drive(Pio *p_pio, uint32_t ul_line,
|
|
enum pio_io_drive_mode mode)
|
|
{
|
|
p_pio->PIO_DRIVER &= ~(1 << ul_line);
|
|
p_pio->PIO_DRIVER |= mode << ul_line;
|
|
}
|
|
#endif
|
|
|
|
#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
|
|
/**
|
|
* \brief Enable PIO keypad controller.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*/
|
|
void pio_keypad_enable(Pio *p_pio)
|
|
{
|
|
p_pio->PIO_KER |= PIO_KER_KCE;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable PIO keypad controller.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*/
|
|
void pio_keypad_disable(Pio *p_pio)
|
|
{
|
|
p_pio->PIO_KER &= (~PIO_KER_KCE);
|
|
}
|
|
|
|
/**
|
|
* \brief Set PIO keypad controller row number.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param num Number of row of the keypad matrix.
|
|
*/
|
|
void pio_keypad_set_row_num(Pio *p_pio, uint8_t num)
|
|
{
|
|
p_pio->PIO_KRCR &= (~PIO_KRCR_NBR_Msk);
|
|
p_pio->PIO_KRCR |= PIO_KRCR_NBR(num);
|
|
}
|
|
|
|
/**
|
|
* \brief Get PIO keypad controller row number.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return Number of row of the keypad matrix.
|
|
*/
|
|
uint8_t pio_keypad_get_row_num(const Pio *p_pio)
|
|
{
|
|
return ((p_pio->PIO_KRCR & PIO_KRCR_NBR_Msk) >> PIO_KRCR_NBR_Pos);
|
|
}
|
|
|
|
/**
|
|
* \brief Set PIO keypad controller column number.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param num Number of column of the keypad matrix.
|
|
*/
|
|
void pio_keypad_set_column_num(Pio *p_pio, uint8_t num)
|
|
{
|
|
p_pio->PIO_KRCR &= (~PIO_KRCR_NBC_Msk);
|
|
p_pio->PIO_KRCR |= PIO_KRCR_NBC(num);
|
|
}
|
|
|
|
/**
|
|
* \brief Get PIO keypad controller column number.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return Number of column of the keypad matrix.
|
|
*/
|
|
uint8_t pio_keypad_get_column_num(const Pio *p_pio)
|
|
{
|
|
return ((p_pio->PIO_KRCR & PIO_KRCR_NBC_Msk) >> PIO_KRCR_NBC_Pos);
|
|
}
|
|
|
|
/**
|
|
* \brief Set PIO keypad matrix debouncing value.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param num Number of debouncing value.
|
|
*/
|
|
void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value)
|
|
{
|
|
p_pio->PIO_KDR = PIO_KDR_DBC(value);
|
|
}
|
|
|
|
/**
|
|
* \brief Get PIO keypad matrix debouncing value.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The keypad debouncing value.
|
|
*/
|
|
uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio)
|
|
{
|
|
return ((p_pio->PIO_KDR & PIO_KDR_DBC_Msk) >> PIO_KDR_DBC_Pos);
|
|
}
|
|
|
|
/**
|
|
* \brief Enable the interrupt source of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Interrupt sources bit map.
|
|
*/
|
|
void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_KIER = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Disable the interrupt source of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param ul_mask Interrupt sources bit map.
|
|
*/
|
|
void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask)
|
|
{
|
|
p_pio->PIO_KIDR = ul_mask;
|
|
}
|
|
|
|
/**
|
|
* \brief Get interrupt mask of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The interrupt mask value.
|
|
*/
|
|
uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio)
|
|
{
|
|
return p_pio->PIO_KIMR;
|
|
}
|
|
|
|
/**
|
|
* \brief Get key press status of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The status of key press.
|
|
* 0: No key press has been detected.
|
|
* 1: At least one key press has been detected.
|
|
*/
|
|
uint32_t pio_keypad_get_press_status(const Pio *p_pio)
|
|
{
|
|
if (p_pio->PIO_KSR & PIO_KSR_KPR) {
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Get key release status of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The status of key release.
|
|
* 0 No key release has been detected.
|
|
* 1 At least one key release has been detected.
|
|
*/
|
|
uint32_t pio_keypad_get_release_status(const Pio *p_pio)
|
|
{
|
|
if (p_pio->PIO_KSR & PIO_KSR_KRL) {
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Get simultaneous key press number of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The number of simultaneous key press.
|
|
*/
|
|
uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio)
|
|
{
|
|
return ((p_pio->PIO_KSR & PIO_KSR_NBKPR_Msk) >> PIO_KSR_NBKPR_Pos);
|
|
}
|
|
|
|
/**
|
|
* \brief Get simultaneous key release number of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
*
|
|
* \return The number of simultaneous key release.
|
|
*/
|
|
uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio)
|
|
{
|
|
return ((p_pio->PIO_KSR & PIO_KSR_NBKRL_Msk) >> PIO_KSR_NBKRL_Pos);
|
|
}
|
|
|
|
/**
|
|
* \brief Get detected key press row index of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param queue The queue of key press row
|
|
*
|
|
* \return The index of detected key press row.
|
|
*/
|
|
uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue)
|
|
{
|
|
switch (queue) {
|
|
case 0:
|
|
return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0ROW_Msk) >> PIO_KKPR_KEY0ROW_Pos);
|
|
case 1:
|
|
return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1ROW_Msk) >> PIO_KKPR_KEY1ROW_Pos);
|
|
case 2:
|
|
return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2ROW_Msk) >> PIO_KKPR_KEY2ROW_Pos);
|
|
case 3:
|
|
return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3ROW_Msk) >> PIO_KKPR_KEY3ROW_Pos);
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Get detected key press column index of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param queue The queue of key press column
|
|
*
|
|
* \return The index of detected key press column.
|
|
*/
|
|
uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue)
|
|
{
|
|
switch (queue) {
|
|
case 0:
|
|
return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0COL_Msk) >> PIO_KKPR_KEY0COL_Pos);
|
|
case 1:
|
|
return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1COL_Msk) >> PIO_KKPR_KEY1COL_Pos);
|
|
case 2:
|
|
return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2COL_Msk) >> PIO_KKPR_KEY2COL_Pos);
|
|
case 3:
|
|
return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3COL_Msk) >> PIO_KKPR_KEY3COL_Pos);
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Get detected key release row index of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param queue The queue of key release row
|
|
*
|
|
* \return The index of detected key release row.
|
|
*/
|
|
uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue)
|
|
{
|
|
switch (queue) {
|
|
case 0:
|
|
return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0ROW_Msk) >> PIO_KKRR_KEY0ROW_Pos);
|
|
case 1:
|
|
return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1ROW_Msk) >> PIO_KKRR_KEY1ROW_Pos);
|
|
case 2:
|
|
return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2ROW_Msk) >> PIO_KKRR_KEY2ROW_Pos);
|
|
case 3:
|
|
return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3ROW_Msk) >> PIO_KKRR_KEY3ROW_Pos);
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Get detected key release column index of PIO keypad.
|
|
*
|
|
* \param p_pio Pointer to a PIO instance.
|
|
* \param queue The queue of key release column
|
|
*
|
|
* \return The index of detected key release column.
|
|
*/
|
|
uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue)
|
|
{
|
|
switch (queue) {
|
|
case 0:
|
|
return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0COL_Msk) >> PIO_KKRR_KEY0COL_Pos);
|
|
case 1:
|
|
return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1COL_Msk) >> PIO_KKRR_KEY1COL_Pos);
|
|
case 2:
|
|
return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2COL_Msk) >> PIO_KKRR_KEY2COL_Pos);
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case 3:
|
|
return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3COL_Msk) >> PIO_KKRR_KEY3COL_Pos);
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
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|
#endif
|
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//@}
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|