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621 lines
14 KiB
C
621 lines
14 KiB
C
/**
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* \file
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*
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* \brief Matrix driver for SAM.
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*
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* Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include "matrix.h"
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/* / @cond 0 */
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/* / @endcond */
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/**
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* \defgroup sam_drivers_matrix_group Matrix (MATRIX)
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*
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* \par Purpose
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*
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* The Bus Matrix implements a multi-layer AHB that enables parallel access
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* paths between multiple AHB masters and slaves in a system, which increases
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* the overall bandwidth.
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*
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* @{
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*/
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#if SAM4C
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#ifdef SAM4C_0
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#define MATRIX MATRIX0
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#else
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#define MATRIX MATRIX1
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#endif
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#endif
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#if SAM4CP
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#ifdef SAM4CP_0
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#define MATRIX MATRIX0
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#else
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#define MATRIX MATRIX1
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#endif
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#endif
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#if SAM4CM
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#ifdef SAM4CM_0
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#define MATRIX MATRIX0
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#else
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#define MATRIX MATRIX1
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#endif
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#endif
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#ifndef MATRIX_WPMR_WPKEY_PASSWD
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#define MATRIX_WPMR_WPKEY_PASSWD MATRIX_WPMR_WPKEY(0x4D4154U)
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#endif
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/**
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* \brief Set undefined length burst type of the specified master.
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*
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* \param ul_id Master index.
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* \param burst_type Undefined length burst type.
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*/
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void matrix_set_master_burst_type(uint32_t ul_id, burst_type_t burst_type)
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{
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#if (SAMV70 || SAMS70|| SAME70)
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Matrix *p_matrix = MATRIX;
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volatile uint32_t *p_MCFG;
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volatile uint32_t ul_reg;
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uint32_t ul_dlt;
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ul_dlt = (uint32_t)&(p_matrix->MATRIX_MCFG1);
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ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_MCFG0);
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p_MCFG = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_MCFG0) +
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ul_id * ul_dlt);
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ul_reg = *p_MCFG & (~MATRIX_MCFG0_ULBT_Msk);
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*p_MCFG = ul_reg | (uint32_t)burst_type;
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#else
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_MCFG[ul_id] & (~MATRIX_MCFG_ULBT_Msk);
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p_matrix->MATRIX_MCFG[ul_id] = ul_reg | (uint32_t)burst_type;
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#endif
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}
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/**
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* \brief Get undefined length burst type of the specified master.
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*
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* \param ul_id Master index.
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*
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* \return Undefined length burst type.
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*/
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burst_type_t matrix_get_master_burst_type(uint32_t ul_id)
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{
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#if (SAMV70 || SAMS70|| SAME70)
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Matrix *p_matrix = MATRIX;
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volatile uint32_t *p_MCFG;
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volatile uint32_t ul_reg;
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uint32_t ul_dlt;
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ul_dlt = (uint32_t)&(p_matrix->MATRIX_MCFG1);
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ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_MCFG0);
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p_MCFG = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_MCFG0) +
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ul_id * ul_dlt);
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ul_reg = *p_MCFG & (~MATRIX_MCFG0_ULBT_Msk);
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return (burst_type_t)ul_reg;
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#else
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_MCFG[ul_id] & (MATRIX_MCFG_ULBT_Msk);
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return (burst_type_t)ul_reg;
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#endif
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}
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/**
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* \brief Set slot cycle of the specified slave.
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*
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* \param ul_id Slave index.
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* \param ul_slot_cycle Number of slot cycle.
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*/
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void matrix_set_slave_slot_cycle(uint32_t ul_id, uint32_t ul_slot_cycle)
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{
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_SLOT_CYCLE_Msk);
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p_matrix->MATRIX_SCFG[ul_id] = ul_reg | MATRIX_SCFG_SLOT_CYCLE(
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ul_slot_cycle);
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}
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/**
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* \brief Get slot cycle of the specified slave.
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*
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* \param ul_id Slave index.
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*
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* \return Number of slot cycle.
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*/
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uint32_t matrix_get_slave_slot_cycle(uint32_t ul_id)
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{
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_SLOT_CYCLE_Msk);
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return (ul_reg >> MATRIX_SCFG_SLOT_CYCLE_Pos);
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}
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/**
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* \brief Set default master type of the specified slave.
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*
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* \param ul_id Slave index.
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* \param type Default master type.
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*/
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void matrix_set_slave_default_master_type(uint32_t ul_id, defaut_master_t type)
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{
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_DEFMSTR_TYPE_Msk);
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p_matrix->MATRIX_SCFG[ul_id] = ul_reg | (uint32_t)type;
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}
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/**
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* \brief Get default master type of the specified slave.
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*
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* \param ul_id Slave index.
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*
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* \return Default master type.
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*/
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defaut_master_t matrix_get_slave_default_master_type(uint32_t ul_id)
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{
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_DEFMSTR_TYPE_Msk);
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return (defaut_master_t)ul_reg;
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}
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/**
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* \brief Set fixed default master of the specified slave.
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*
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* \param ul_id Slave index.
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* \param ul_fixed_id Fixed default master index.
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*/
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void matrix_set_slave_fixed_default_master(uint32_t ul_id, uint32_t ul_fixed_id)
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{
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_SCFG[ul_id] &
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(~MATRIX_SCFG_FIXED_DEFMSTR_Msk);
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p_matrix->MATRIX_SCFG[ul_id]
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= ul_reg | MATRIX_SCFG_FIXED_DEFMSTR(ul_fixed_id);
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}
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/**
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* \brief Get fixed default master of the specified slave.
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*
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* \param ul_id Slave index.
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*
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* \return Fixed default master index.
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*/
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uint32_t matrix_get_slave_fixed_default_master(uint32_t ul_id)
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{
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_FIXED_DEFMSTR_Msk);
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return (ul_reg >> MATRIX_SCFG_FIXED_DEFMSTR_Pos);
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}
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#if !SAM4E && !SAM4C && !SAM4CP && !SAM4CM && \
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!SAMV71 && !SAMV70 && !SAMS70 && !SAME70
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/**
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* \brief Set slave arbitration type of the specified slave.
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*
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* \param ul_id Slave index.
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* \param type Arbitration type.
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*/
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void matrix_set_slave_arbitration_type(uint32_t ul_id, arbitration_type_t type)
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{
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_ARBT_Msk);
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p_matrix->MATRIX_SCFG[ul_id] = ul_reg | (uint32_t)type;
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}
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/**
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* \brief Get slave arbitration type of the specified slave.
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*
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* \param ul_id Slave index.
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*
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* \return Arbitration type.
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*/
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arbitration_type_t matrix_get_slave_arbitration_type(uint32_t ul_id)
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{
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Matrix *p_matrix = MATRIX;
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volatile uint32_t ul_reg;
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ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_ARBT_Msk);
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return (arbitration_type_t)ul_reg;
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}
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#endif
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/**
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* \brief Set priority for the specified slave access.
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*
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* \param ul_id Slave index.
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* \param ul_prio Bitmask OR of priorities of master x.
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*/
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void matrix_set_slave_priority(uint32_t ul_id, uint32_t ul_prio)
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{
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#if (SAMV71 || SAMV70|| SAME70)
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Matrix *p_matrix = MATRIX;
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p_matrix->MATRIX_PR[ul_id].MATRIX_PRAS = ul_prio;
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#else
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Matrix *p_matrix = MATRIX;
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volatile uint32_t *p_PRAS;
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uint32_t ul_dlt;
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ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRAS1);
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ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRAS0);
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p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRAS0) +
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ul_id * ul_dlt);
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*p_PRAS = ul_prio;
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#endif
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}
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/**
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* \brief Get priority for the specified slave access.
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*
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* \param ul_id Slave index.
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*
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* \return Bitmask OR of priorities of master x.
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*/
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uint32_t matrix_get_slave_priority(uint32_t ul_id)
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{
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#if (SAMV71 || SAMV70|| SAME70)
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Matrix *p_matrix = MATRIX;
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return p_matrix->MATRIX_PR[ul_id].MATRIX_PRAS;
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#else
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Matrix *p_matrix = MATRIX;
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volatile uint32_t *p_PRAS;
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uint32_t ul_dlt;
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ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRAS1);
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ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRAS0);
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p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRAS0) +
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ul_id * ul_dlt);
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return (*p_PRAS);
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#endif
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}
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#if (SAMV71 || SAMV70|| SAME70 || SAMS70)
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/**
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* \brief Set priority for the specified slave access.
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*
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* \param ul_id Slave index.
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* \param ul_prio_b Bitmask OR of priorities of master x.
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*/
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void matrix_set_slave_priority_b(uint32_t ul_id, uint32_t ul_prio_b)
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{
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#if (SAMV71 || SAMV70|| SAME70)
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Matrix *p_matrix = MATRIX;
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p_matrix->MATRIX_PR[ul_id].MATRIX_PRBS = ul_prio_b;
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#else
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Matrix *p_matrix = MATRIX;
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volatile uint32_t *p_PRAS;
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uint32_t ul_dlt;
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ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRBS1);
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ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRBS0);
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p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRBS0) +
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ul_id * ul_dlt);
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*p_PRAS = ul_prio;
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#endif
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}
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/**
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* \brief Get priority for the specified slave access.
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*
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* \param ul_id Slave index.
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*
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* \return Bitmask OR of priorities of master x.
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*/
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uint32_t matrix_get_slave_priority_b(uint32_t ul_id)
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{
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#if (SAMV71 || SAMV70|| SAME70)
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Matrix *p_matrix = MATRIX;
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return p_matrix->MATRIX_PR[ul_id].MATRIX_PRBS;
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#else
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Matrix *p_matrix = MATRIX;
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volatile uint32_t *p_PRAS;
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uint32_t ul_dlt;
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ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRBS1);
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ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRBS0);
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p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRBS0) +
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ul_id * ul_dlt);
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return (*p_PRAS);
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#endif
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}
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#endif
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#if (SAM3XA || SAM3U || SAM4E ||\
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SAMV71 || SAMV70 || SAMS70 || SAME70)
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/**
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* \brief Set bus matrix master remap.
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*
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* \param ul_remap Bitmask OR of RCBx: 0 for disable, 1 for enable.
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*/
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void matrix_set_master_remap(uint32_t ul_remap)
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{
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Matrix *p_matrix = MATRIX;
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p_matrix->MATRIX_MRCR = ul_remap;
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}
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/**
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* \brief Get bus matrix master remap.
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*
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* \return Bitmask OR of RCBx: 0 for disable, 1 for enable.
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*/
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uint32_t matrix_get_master_remap(void)
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{
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Matrix *p_matrix = MATRIX;
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return (p_matrix->MATRIX_MRCR);
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}
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#endif
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#if (SAM3S || SAM3XA || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \
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SAMV71 || SAMV70 || SAMS70 || SAME70)
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/**
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* \brief Set system IO.
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*
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* \param ul_io Bitmask OR of SYSIOx.
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*/
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void matrix_set_system_io(uint32_t ul_io)
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{
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Matrix *p_matrix = MATRIX;
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#if (SAM4C || SAM4CP || SAM4CM)
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p_matrix->MATRIX_SYSIO = ul_io;
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#elif (SAMV71 || SAMV70 || SAMS70 || SAME70)
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p_matrix->CCFG_SYSIO &= 0xFFFF0000;
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p_matrix->CCFG_SYSIO |= (ul_io & 0xFFFF);
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#else
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p_matrix->CCFG_SYSIO = ul_io;
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#endif
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}
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/**
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* \brief Get system IO.
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*
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* \return Bitmask OR of SYSIOx.
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*/
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uint32_t matrix_get_system_io(void)
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{
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Matrix *p_matrix = MATRIX;
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#if (SAM4C || SAM4CP || SAM4CM)
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return (p_matrix->MATRIX_SYSIO);
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#elif (SAMV71 || SAMV70 || SAMS70 || SAME70)
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return (p_matrix->CCFG_SYSIO & 0xFFFF);
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#else
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return (p_matrix->CCFG_SYSIO);
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#endif
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}
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#endif
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#if (SAM3S || SAM4S || SAM4E || SAM4C || SAM4CP || SAM4CM || \
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SAMV71 || SAMV70 || SAMS70 || SAME70)
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/**
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* \brief Set NAND Flash Chip Select configuration register.
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*
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* \param ul_cs Bitmask OR of SMC_NFCSx: 0 if NCSx is not assigned,
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* 1 if NCSx is assigned.
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*/
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void matrix_set_nandflash_cs(uint32_t ul_cs)
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{
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Matrix *p_matrix = MATRIX;
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#if (SAM4C || SAM4CP || SAM4CM)
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p_matrix->MATRIX_SMCNFCS = ul_cs;
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#else
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p_matrix->CCFG_SMCNFCS = ul_cs;
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#endif
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|
}
|
|
|
|
/**
|
|
* \brief Get NAND Flash Chip Select configuration register.
|
|
*
|
|
* \return Bitmask OR of SMC_NFCSx.
|
|
*/
|
|
uint32_t matrix_get_nandflash_cs(void)
|
|
{
|
|
Matrix *p_matrix = MATRIX;
|
|
|
|
#if (SAM4C || SAM4CP || SAM4CM)
|
|
|
|
return (p_matrix->MATRIX_SMCNFCS);
|
|
|
|
#else
|
|
|
|
return (p_matrix->CCFG_SMCNFCS);
|
|
|
|
#endif
|
|
}
|
|
|
|
#endif
|
|
|
|
#if (!SAMG)
|
|
/**
|
|
* \brief Enable or disable write protect of MATRIX registers.
|
|
*
|
|
* \param ul_enable 1 to enable, 0 to disable.
|
|
*/
|
|
void matrix_set_writeprotect(uint32_t ul_enable)
|
|
{
|
|
Matrix *p_matrix = MATRIX;
|
|
|
|
if (ul_enable) {
|
|
p_matrix->MATRIX_WPMR = MATRIX_WPMR_WPKEY_PASSWD | MATRIX_WPMR_WPEN;
|
|
} else {
|
|
p_matrix->MATRIX_WPMR = MATRIX_WPMR_WPKEY_PASSWD;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Get write protect status.
|
|
*
|
|
* \return Write protect status.
|
|
*/
|
|
uint32_t matrix_get_writeprotect_status(void)
|
|
{
|
|
Matrix *p_matrix = MATRIX;
|
|
|
|
return (p_matrix->MATRIX_WPSR);
|
|
}
|
|
#endif
|
|
|
|
#if SAMG55
|
|
/**
|
|
* \brief Set USB device mode.
|
|
*
|
|
*/
|
|
void matrix_set_usb_device(void)
|
|
{
|
|
Matrix *p_matrix = MATRIX;
|
|
|
|
p_matrix->CCFG_SYSIO &= ~(CCFG_SYSIO_SYSIO10 | CCFG_SYSIO_SYSIO11);
|
|
|
|
p_matrix->CCFG_USBMR |= CCFG_USBMR_DEVICE;
|
|
}
|
|
|
|
/**
|
|
* \brief Set USB device mode.
|
|
*
|
|
*/
|
|
void matrix_set_usb_host(void)
|
|
{
|
|
Matrix *p_matrix = MATRIX;
|
|
|
|
p_matrix->CCFG_SYSIO &= ~(CCFG_SYSIO_SYSIO10 | CCFG_SYSIO_SYSIO11);
|
|
|
|
p_matrix->CCFG_USBMR &= ~CCFG_USBMR_DEVICE;
|
|
}
|
|
#endif
|
|
|
|
#if (SAMV71 || SAMV70|| SAME70)
|
|
/**
|
|
* \brief Set CAN0 DMA base address.
|
|
*
|
|
* \param base_addr the 16-bit MSB of the CAN0 DMA base address.
|
|
*/
|
|
void matrix_set_can0_addr(uint32_t base_addr)
|
|
{
|
|
Matrix *p_matrix = MATRIX;
|
|
p_matrix->CCFG_CAN0 = CCFG_CAN0_CAN0DMABA(base_addr);
|
|
}
|
|
|
|
/**
|
|
* \brief Set CAN1 DMA base address.
|
|
*
|
|
* \param base_addr the 16-bit MSB of the CAN1 DMA base address.
|
|
*/
|
|
void matrix_set_can1_addr(uint32_t base_addr)
|
|
{
|
|
Matrix *p_matrix = MATRIX;
|
|
volatile uint32_t ul_reg;
|
|
|
|
ul_reg = p_matrix->CCFG_SYSIO & (~CCFG_SYSIO_CAN1DMABA_Msk);
|
|
p_matrix->CCFG_SYSIO = ul_reg | CCFG_SYSIO_CAN1DMABA(base_addr);
|
|
}
|
|
#endif
|
|
|
|
/* @} */
|
|
|
|
/* / @cond 0 */
|
|
/**INDENT-OFF**/
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
/**INDENT-ON**/
|
|
/* / @endcond */
|