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stm32-l053r8-em9304: send '0's when reading SPI data
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@ -161,10 +161,13 @@ static volatile enum {
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} hal_spi_em9304_state;
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} hal_spi_em9304_state;
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#define SPI_EM9304_RX_BUFFER_SIZE 64
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#define SPI_EM9304_RX_BUFFER_SIZE 64
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#define SPI_EM9304_TX_BUFFER_SIZE 64
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#define SPI_EM9304_RING_BUFFER_SIZE 128
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#define SPI_EM9304_RING_BUFFER_SIZE 128
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static uint8_t hal_spi_em9304_slave_status[2];
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static uint8_t hal_spi_em9304_slave_status[2];
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static const uint8_t hal_spi_em9304_zeros[SPI_EM9304_TX_BUFFER_SIZE];
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static uint8_t hal_spi_em9304_rx_buffer[SPI_EM9304_RX_BUFFER_SIZE];
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static uint8_t hal_spi_em9304_rx_buffer[SPI_EM9304_RX_BUFFER_SIZE];
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static uint16_t hal_spi_em9304_rx_request_len;
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static uint16_t hal_spi_em9304_rx_request_len;
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static uint16_t hal_spi_em9304_tx_request_len;
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static uint16_t hal_spi_em9304_tx_request_len;
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@ -206,6 +209,10 @@ void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi){
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hal_spi_em9304_state = SPI_EM9304_TX_WRITE_COMMAND_SENT;
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hal_spi_em9304_state = SPI_EM9304_TX_WRITE_COMMAND_SENT;
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hal_spi_em9304_trigger_run_loop();
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hal_spi_em9304_trigger_run_loop();
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break;
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break;
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case SPI_EM9304_RX_W4_DATA_RECEIVED:
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hal_spi_em9304_state = SPI_EM9304_RX_DATA_RECEIVED;
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hal_spi_em9304_trigger_run_loop();
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break;
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default:
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default:
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break;
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break;
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}
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}
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@ -303,10 +310,10 @@ static void hal_spi_em9304_process(btstack_data_source_t *ds, btstack_data_sourc
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break;
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break;
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}
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}
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// read all data
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// read data and send '0's
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hal_spi_em9304_state = SPI_EM9304_RX_W4_DATA_RECEIVED;
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hal_spi_em9304_state = SPI_EM9304_RX_W4_DATA_RECEIVED;
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hal_spi_em9304_rx_request_len = hal_spi_em9304_slave_status[1];
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hal_spi_em9304_rx_request_len = hal_spi_em9304_slave_status[1];
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HAL_SPI_Receive_DMA(&hspi1, &hal_spi_em9304_rx_buffer[0], hal_spi_em9304_rx_request_len);
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HAL_SPI_TransmitReceive_DMA(&hspi1, (uint8_t*) hal_spi_em9304_zeros, &hal_spi_em9304_rx_buffer[0], hal_spi_em9304_rx_request_len);
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break;
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break;
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case SPI_EM9304_RX_DATA_RECEIVED:
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case SPI_EM9304_RX_DATA_RECEIVED:
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