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https://github.com/bluekitchen/btstack.git
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renesas-tb-s1ja: reduce heap from 0x1000 to 0x100
This commit is contained in:
Matthias Ringwald
parent
b1a0b198f1
commit
afbbff0576
@ -0,0 +1,311 @@
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/*
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Linker File for S1JA MCU
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*/
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/* Linker script to configure memory regions. */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* 256K */
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x008000 /* 32K */
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DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x0002000 /* 8K */
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ID_CODE_1 (rx) : ORIGIN = 0x01010018, LENGTH = 0x04 /* 4 bytes */
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ID_CODE_2 (rx) : ORIGIN = 0x01010020, LENGTH = 0x04 /* 4 bytes */
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ID_CODE_3 (rx) : ORIGIN = 0x01010028, LENGTH = 0x04 /* 4 bytes */
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ID_CODE_4 (rx) : ORIGIN = 0x01010030, LENGTH = 0x04 /* 4 bytes */
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}
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/* Library configurations */
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GROUP(libgcc.a libc.a libm.a libnosys.a)
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __copy_table_start__
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* __copy_table_end__
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* __zero_table_start__
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* __zero_table_end__
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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* __Vectors_End
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* __Vectors_Size
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*/
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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__ROM_Start = .;
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/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
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* space because ROM registers are at address 0x400 and there is very little space
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* in between. */
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KEEP(*(.vectors))
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KEEP(*(SORT_BY_NAME(.vector.*)))
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__Vectors_End = .;
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__end__ = .;
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/* ROM Registers start at address 0x00000400 */
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. = __ROM_Start + 0x400;
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KEEP(*(.rom_registers*))
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/* Reserving 0x100 bytes of space for ROM registers. */
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. = __ROM_Start + 0x500;
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/* Vector information array. */
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__Vector_Info_Start = .;
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KEEP(*(SORT_BY_NAME(.vector_info.*)))
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__Vector_Info_End = .;
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/* Hardware lock lookup array. */
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__Lock_Lookup_Start = .;
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KEEP(*(SORT_BY_NAME(.hw_lock_lookup.*)))
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__Lock_Lookup_End = .;
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata*)
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__usb_dev_descriptor_start_fs = .;
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KEEP(*(.usb_device_desc_fs*))
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__usb_cfg_descriptor_start_fs = .;
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KEEP(*(.usb_config_desc_fs*))
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__usb_interface_descriptor_start_fs = .;
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KEEP(*(.usb_interface_desc_fs*))
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__usb_descriptor_end_fs = .;
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KEEP(*(.eh_frame*))
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__ROM_End = .;
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} > FLASH = 0xFF
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__Vectors_Size = __Vectors_End - __Vectors;
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__Vector_Info_Size = __Vector_Info_End - __Vector_Info_Start;
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__Lock_Lookup_Size = __Lock_Lookup_End - __Lock_Lookup_Start;
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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/* To copy multiple ROM to RAM sections,
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* uncomment .copy.table section and,
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* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
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/*
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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LONG (__etext2)
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LONG (__data2_start__)
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LONG (__data2_end__ - __data2_start__)
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__copy_table_end__ = .;
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} > FLASH
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*/
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/* To clear multiple BSS sections,
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* uncomment .zero.table section and,
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* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
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/*
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG (__bss_end__ - __bss_start__)
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LONG (__bss2_start__)
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LONG (__bss2_end__ - __bss2_start__)
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__zero_table_end__ = .;
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} > FLASH
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*/
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__etext = .;
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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.ssp_dtc_vector_table (NOLOAD) :
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{
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. = ORIGIN(RAM);
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*(.ssp_dtc_vector_table)
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} > RAM
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/* Initialized data section. */
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.data :
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{
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__data_start__ = .;
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*(vtable)
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*(.data.*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(4);
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__Code_In_RAM_Start = .;
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KEEP(*(.code_in_ram*))
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__Code_In_RAM_End = .;
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/* Hardware look array. */
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__Lock_Start = .;
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KEEP(*(SORT_BY_NAME(.hw_lock*)))
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__Lock_End = .;
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/* All data end */
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__data_end__ = .;
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} > RAM AT > FLASH
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__Lock_Size = __Lock_End - __Lock_Start;
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.noinit (NOLOAD):
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{
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. = ALIGN(4);
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__noinit_start = .;
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KEEP(*(.noinit*))
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__noinit_end = .;
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} > RAM
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.bss :
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{
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > RAM
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.heap (NOLOAD):
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{
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. = ALIGN(8);
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__HeapBase = .;
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__end__ = .;
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end = __end__;
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KEEP(*(.heap*))
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__HeapLimit = .;
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} > RAM
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/* Stacks are stored in this section. */
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.stack_dummy (NOLOAD):
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{
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. = ALIGN(8);
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__StackLimit = .;
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/* Main stack */
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KEEP(*(.stack))
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__StackTop = .;
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/* Thread stacks */
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KEEP(*(.stack*))
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__StackTopAll = .;
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} > RAM
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PROVIDE(__stack = __StackTopAll);
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/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
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at run time for things such as ThreadX memory pool allocations. */
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__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
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/* Data flash. */
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.data_flash :
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{
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__Data_Flash_Start = .;
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KEEP(*(.data_flash*))
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__Data_Flash_End = .;
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} > DATA_FLASH
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.id_code_1 :
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{
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__ID_Code_1_Start = .;
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KEEP(*(.id_code_1*))
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__ID_Code_1_End = .;
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} > ID_CODE_1
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.id_code_2 :
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{
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__ID_Code_2_Start = .;
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KEEP(*(.id_code_2*))
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__ID_Code_2_End = .;
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} > ID_CODE_2
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.id_code_3 :
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{
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__ID_Code_3_Start = .;
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KEEP(*(.id_code_3*))
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__ID_Code_3_End = .;
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} > ID_CODE_3
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.id_code_4 :
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{
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__ID_Code_4_Start = .;
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KEEP(*(.id_code_4*))
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__ID_Code_4_End = .;
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} > ID_CODE_4
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}
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@ -0,0 +1,40 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "bsp_board_cfg.h"
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#define SYNERGY_NOT_DEFINED 0
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#if (SYNERGY_NOT_DEFINED) == (SYNERGY_NOT_DEFINED)
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#define BSP_CFG_RTOS (0)
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#else
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#define BSP_CFG_RTOS (1)
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#endif
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#undef SYNERGY_NOT_DEFINED
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_MCU_AVCC0_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
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#define BSP_CFG_STACK_PROCESS_BYTES (0)
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#define BSP_CFG_HEAP_BYTES (0x100)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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/*
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ID Code
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Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
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WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
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*/
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#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
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#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
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#else
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/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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#endif /* BSP_CFG_H_ */
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