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chipset/nxp: configure I2S, 2048 kHz, left channel

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This commit is contained in:
Matthias Ringwald 2023-08-15 16:58:44 +02:00
parent 3f6e1c8176
commit 938a5e841b
1 changed files with 32 additions and 1 deletions
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33
chipset/nxp/btstack_chipset_nxp.c
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@ -453,6 +453,10 @@ void btstack_chipset_nxp_download_firmware_with_uart(const btstack_uart_t *uart_
// init script support // init script support
static enum { static enum {
NXP_INIT_SEND_SCO_CONFIG, NXP_INIT_SEND_SCO_CONFIG,
NXP_INIT_SEND_HOST_CONTROL_ENABLE,
NXP_INIT_SEND_WRITE_PCM_SETTINGS,
NXP_INIT_SEND_WRITE_PCM_SYNC_SETTINGS,
NXP_INIT_SEND_WRITE_PCM_LINK_SETTINGS,
NXP_INIT_DONE, NXP_INIT_DONE,
} nxp_init_state; } nxp_init_state;
@ -475,9 +479,36 @@ static btstack_chipset_result_t nxp_next_command(uint8_t * hci_cmd_buffer) {
switch (nxp_init_state){ switch (nxp_init_state){
case NXP_INIT_SEND_SCO_CONFIG: case NXP_INIT_SEND_SCO_CONFIG:
#if defined(ENABLE_SCO_OVER_HCI) || defined(ENABLE_SCO_OVER_PCM) #if defined(ENABLE_SCO_OVER_HCI) || defined(ENABLE_SCO_OVER_PCM)
nxp_init_state = NXP_INIT_DONE; nxp_init_state = NXP_INIT_SEND_HOST_CONTROL_ENABLE;
hci_cmd_create_from_template_with_vargs(hci_cmd_buffer, &hci_nxp_set_sco_data_path, nxp_chipset_sco_routing_path); hci_cmd_create_from_template_with_vargs(hci_cmd_buffer, &hci_nxp_set_sco_data_path, nxp_chipset_sco_routing_path);
return BTSTACK_CHIPSET_VALID_COMMAND; return BTSTACK_CHIPSET_VALID_COMMAND;
#endif
#ifdef ENABLE_SCO_OVER_PCM
case NXP_INIT_SEND_HOST_CONTROL_ENABLE:
nxp_init_state = NXP_INIT_SEND_WRITE_PCM_SETTINGS;
// Host Control enabled
hci_cmd_create_from_template_with_vargs(hci_cmd_buffer, &hci_nxp_host_pcm_i2s_control_enable, 1);
return BTSTACK_CHIPSET_VALID_COMMAND;
case NXP_INIT_SEND_WRITE_PCM_SETTINGS:
nxp_init_state = NXP_INIT_SEND_WRITE_PCM_SYNC_SETTINGS;
// PCM/I2S master mode
hci_cmd_create_from_template_with_vargs(hci_cmd_buffer, &hci_nxp_write_pcm_i2s_settings, 0x02);
return BTSTACK_CHIPSET_VALID_COMMAND;
case NXP_INIT_SEND_WRITE_PCM_SYNC_SETTINGS:
nxp_init_state = NXP_INIT_SEND_WRITE_PCM_LINK_SETTINGS;
#ifdef ENABLE_NXP_PCM_WBS
// 16 kHz sync, 2048 kHz, data in left channel, DIN sampled on rising edge, DOUT driven on falling edge, I2Sa
hci_cmd_create_from_template_with_vargs(hci_cmd_buffer, &hci_nxp_write_pcm_i2s_sync_settings, 0x03, 0x071e);
#else
// 8 kHz sync, 2048 kHz, data in left channel, DIN sampled on rising edge, DOUT driven on falling edge, I2S
hci_cmd_create_from_template_with_vargs(hci_cmd_buffer, &hci_nxp_write_pcm_i2s_sync_settings, 0x03, 0x031e);
#endif
return BTSTACK_CHIPSET_VALID_COMMAND;
case NXP_INIT_SEND_WRITE_PCM_LINK_SETTINGS:
nxp_init_state = NXP_INIT_DONE;
// 1st SCO Link PCM Logical Slot 0, PCM start slot 1
hci_cmd_create_from_template_with_vargs(hci_cmd_buffer, &hci_nxp_write_pcm_link_settings, 0x0004);
return BTSTACK_CHIPSET_VALID_COMMAND;
#endif #endif
default: default:
break; break;