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hci_transport_h4_ehcill_dma: use HCI_OUTGOING_PRE_BUFFER_SIZE
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@ -57,9 +57,10 @@
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#include <btstack/run_loop.h>
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#include <btstack/hal_uart_dma.h>
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// #include <libopencm3/stm32/gpio.h>
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// #define GPIO_DEBUG_0 GPIO1
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// #define GPIO_DEBUG_1 GPIO2
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// assert pre-buffer for packet type is available
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#if !defined(HCI_OUTGOING_PRE_BUFFER_SIZE) || (HCI_OUTGOING_PRE_BUFFER_SIZE == 0)
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#error HCI_OUTGOING_PRE_BUFFER_SIZE not defined. Please update hci.h
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#endif
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// #define LOG_EHCILL
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@ -81,7 +82,6 @@ typedef enum {
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typedef enum {
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TX_IDLE = 1,
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TX_W4_WAKEUP, // eHCILL only
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TX_W4_HEADER_SENT,
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TX_W4_PACKET_SENT,
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TX_W2_EHCILL_SEND,
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TX_W4_EHCILL_SENT,
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@ -137,9 +137,8 @@ static void (*packet_handler)(uint8_t packet_type, uint8_t *packet, uint16_t si
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// H4: tx state
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static volatile TX_STATE tx_state; // updated from block_sent callback
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static volatile int tx_send_packet_sent; // updated from block_sent callback
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static uint8_t tx_packet_type; // 0 == no outgoing packet
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static uint8_t * tx_data;
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static uint16_t tx_len;
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static uint16_t tx_len; // 0 == no outgoing packet
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// work around for eHCILL problem
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static timer_source_t ehcill_sleep_ack_timer;
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@ -203,7 +202,7 @@ static int h4_open(void *transport_config){
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// init state machines
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h4_rx_init_sm();
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tx_state = TX_IDLE;
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tx_packet_type = 0;
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tx_len = 0;
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return 0;
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}
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@ -302,7 +301,7 @@ static int h4_can_send_packet_now(uint8_t packet_type){
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}
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static int h4_outgoing_packet_ready(void){
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return tx_packet_type != 0;
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return tx_len != 0;
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}
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static void ehcill_sleep_ack_timer_handler(timer_source_t * timer){
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@ -344,14 +343,9 @@ static void echill_send_wakeup_ind(void){
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static void h4_block_sent(void){
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int command;
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switch (tx_state){
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case TX_W4_HEADER_SENT:
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tx_state = TX_W4_PACKET_SENT;
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// h4 packet type + actual packet
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hal_uart_dma_send_block(tx_data, tx_len);
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break;
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case TX_W4_PACKET_SENT:
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// packet fully sent, reset state
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tx_packet_type = 0;
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tx_len = 0;
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// now, send pending ehcill command if neccessary
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switch (ehcill_command_to_send){
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case EHCILL_GO_TO_SLEEP_ACK:
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@ -508,8 +502,8 @@ static void ehcill_handle(uint8_t action){
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#ifdef LOG_EHCILL
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log_info("EHCILL: WAKE_UP_IND or ACK");
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#endif
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tx_state = TX_W4_HEADER_SENT;
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hal_uart_dma_send_block(&tx_packet_type, 1);
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tx_state = TX_W4_PACKET_SENT;
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hal_uart_dma_send_block(tx_data, tx_len);
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ehcill_state = EHCILL_STATE_AWAKE;
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break;
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@ -526,7 +520,6 @@ static int ehcill_send_packet(uint8_t packet_type, uint8_t *packet, int size){
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// check for ongoing write
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switch (tx_state){
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case TX_W4_WAKEUP:
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case TX_W4_HEADER_SENT:
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case TX_W4_PACKET_SENT:
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// we should not arrive here, log state
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log_error("h4_send_packet with tx_state = %u, ehcill_state %u, packet type %u, data %02x %02x %02x", tx_state, ehcill_state, packet_type, packet[0], packet[1], packet[2]);
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@ -538,15 +531,19 @@ static int ehcill_send_packet(uint8_t packet_type, uint8_t *packet, int size){
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break;
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}
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// store packet type before actual data and increase size
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size++;
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packet--;
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*packet = packet_type;
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// store request
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tx_packet_type = packet_type;
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tx_data = packet;
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tx_len = size;
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// if awake, just start sending
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if (!ehcill_sleep_mode_active()){
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tx_state = TX_W4_HEADER_SENT;
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hal_uart_dma_send_block(&tx_packet_type, 1);
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tx_state = TX_W4_PACKET_SENT;
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hal_uart_dma_send_block(tx_data, tx_len);
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return 0;
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}
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