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handle case where SLEEP_IND might be received right after regular packet has been sent -> also wait a bit before SLEEP_ACK

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matthias.ringwald@gmail.com 2014-10-16 21:51:46 +00:00
parent 8f837ea3d3
commit 500c418fcd
1 changed files with 11 additions and 9 deletions
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20
src/hci_transport_h4_ehcill_dma.c
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@ -85,6 +85,7 @@ typedef enum {
TX_W4_WAKEUP, // eHCILL only TX_W4_WAKEUP, // eHCILL only
TX_W4_HEADER_SENT, TX_W4_HEADER_SENT,
TX_W4_PACKET_SENT, TX_W4_PACKET_SENT,
TX_W2_EHCILL_SEND,
TX_W4_EHCILL_SENT, TX_W4_EHCILL_SENT,
TX_DONE TX_DONE
} TX_STATE; } TX_STATE;
@ -410,19 +411,20 @@ static void ehcill_cts_irq_handler(){
} }
static void ehcill_schedule_ecill_command(uint8_t command){ static void ehcill_schedule_ecill_command(uint8_t command){
// reply with HCILL_SLEEP_ACK
ehcill_command_to_send = command; ehcill_command_to_send = command;
switch (tx_state){ switch (tx_state){
case TX_IDLE: case TX_IDLE:
// new: change state so BTstack cannot send
// new: setup timer;
// new: break
case TX_DONE: case TX_DONE:
if (ehcill_command_to_send == EHCILL_WAKE_UP_ACK){
// send right away
// gpio_clear(GPIOB, GPIO_DEBUG_1); // gpio_clear(GPIOB, GPIO_DEBUG_1);
tx_state = TX_W4_EHCILL_SENT; tx_state = TX_W4_EHCILL_SENT;
hal_uart_dma_send_block(&ehcill_command_to_send, 1); hal_uart_dma_send_block(&ehcill_command_to_send, 1);
break;
}
// change state so BTstack cannot send and setup timer
tx_state = TX_W2_EHCILL_SEND;
ehcill_sleep_ack_timer_setup();
break; break;
default: default:
break; break;