From 35dfa651882c8c9578ebb4d8c951d2ec91f8f2e1 Mon Sep 17 00:00:00 2001 From: Matthias Ringwald Date: Fri, 29 Apr 2016 14:05:32 +0200 Subject: [PATCH] csr: enable RTS/CTS for BCSP and H5 --- chipset/csr/btstack_chipset_csr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/chipset/csr/btstack_chipset_csr.c b/chipset/csr/btstack_chipset_csr.c index 83bcbf04d..f9f6177c4 100644 --- a/chipset/csr/btstack_chipset_csr.c +++ b/chipset/csr/btstack_chipset_csr.c @@ -71,6 +71,12 @@ static const uint8_t init_script[] = { 0x01, 0x00, 0xFC, 0x13, 0xc2, 0x02, 0x00, 0x09, 0x00, 0x01, 0x00, 0x03, 0x70, 0x00, 0x00, 0xc9, 0x22, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, #endif + // Enable RTS/CTS for BCSP (0806 -> 080e) + 0x01, 0x00, 0xFC, 0x13, 0xc2, 0x02, 0x00, 0x09, 0x00, 0x01, 0x00, 0x03, 0x70, 0x00, 0x00, 0xbf, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0e, 0x08, + + // Enable RTS/CTS for H5 (1806 -> 180e, even parity still on) + 0x01, 0x00, 0xFC, 0x13, 0xc2, 0x02, 0x00, 0x09, 0x00, 0x01, 0x00, 0x03, 0x70, 0x00, 0x00, 0xc1, 0x01, 0x01, 0x00, 0x00, 0x00, 0x0e, 0x08, + // Set UART baudrate to 115200 0x01, 0x00, 0xFC, 0x15, 0xc2, 0x02, 0x00, 0x0a, 0x00, 0x02, 0x00, 0x03, 0x70, 0x00, 0x00, 0xea, 0x01, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xc2,