mirror of
https://github.com/pine64/bl_iot_sdk.git
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201 lines
6.5 KiB
C
201 lines
6.5 KiB
C
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/*
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* Copyright (c) 2020 Bouffalolab.
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*
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* This file is part of
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* *** Bouffalolab Software Dev Kit ***
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* (see www.bouffalolab.com).
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RWNX_RX_H_
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#define _RWNX_RX_H_
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#include "bl_defs.h"
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#include "lmac_types.h"
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enum rx_status_bits
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{
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/// The buffer can be forwarded to the networking stack
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RX_STAT_FORWARD = 1 << 0,
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/// A new buffer has to be allocated
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RX_STAT_ALLOC = 1 << 1,
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/// The buffer has to be deleted
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RX_STAT_DELETE = 1 << 2,
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/// The length of the buffer has to be updated
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RX_STAT_LEN_UPDATE = 1 << 3,
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/// The length in the Ethernet header has to be updated
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RX_STAT_ETH_LEN_UPDATE = 1 << 4,
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/// Simple copy
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RX_STAT_COPY = 1 << 5,
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};
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/*
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* Decryption status subfields.
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* {
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*/
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#define RWNX_RX_HD_DECR_UNENC 0 // Frame unencrypted
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#define RWNX_RX_HD_DECR_ICVFAIL 1 // WEP/TKIP ICV failure
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#define RWNX_RX_HD_DECR_CCMPFAIL 2 // CCMP failure
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#define RWNX_RX_HD_DECR_AMSDUDISCARD 3 // A-MSDU discarded at HW
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#define RWNX_RX_HD_DECR_NULLKEY 4 // NULL key found
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#define RWNX_RX_HD_DECR_WEPSUCCESS 5 // Security type WEP
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#define RWNX_RX_HD_DECR_TKIPSUCCESS 6 // Security type TKIP
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#define RWNX_RX_HD_DECR_CCMPSUCCESS 7 // Security type CCMP
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// @}
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struct hw_vect {
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/** Total length for the MPDU transfer */
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u32 len :16;
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u32 reserved : 8;
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/** AMPDU Status Information */
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u32 mpdu_cnt : 6;
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u32 ampdu_cnt : 2;
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/** TSF Low */
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__le32 tsf_lo;
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/** TSF High */
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__le32 tsf_hi;
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/** Receive Vector 1a */
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u32 leg_length :12;
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u32 leg_rate : 4;
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u32 ht_length :16;
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/** Receive Vector 1b */
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u32 _ht_length : 4; // FIXME
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u32 short_gi : 1;
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u32 stbc : 2;
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u32 smoothing : 1;
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u32 mcs : 7;
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u32 pre_type : 1;
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u32 format_mod : 3;
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u32 ch_bw : 2;
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u32 n_sts : 3;
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u32 lsig_valid : 1;
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u32 sounding : 1;
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u32 num_extn_ss : 2;
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u32 aggregation : 1;
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u32 fec_coding : 1;
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u32 dyn_bw : 1;
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u32 doze_not_allowed : 1;
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/** Receive Vector 1c */
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u32 antenna_set : 8;
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u32 partial_aid : 9;
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u32 group_id : 6;
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u32 reserved_1c : 1;
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s32 rssi1 : 8;
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/** Receive Vector 1d */
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s32 rssi2 : 8;
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s32 rssi3 : 8;
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s32 rssi4 : 8;
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u32 reserved_1d : 8;
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/** Receive Vector 2a */
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u32 rcpi : 8;
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u32 evm1 : 8;
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u32 evm2 : 8;
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u32 evm3 : 8;
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/** Receive Vector 2b */
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u32 evm4 : 8;
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u32 reserved2b_1 : 8;
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u32 reserved2b_2 : 8;
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u32 reserved2b_3 : 8;
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/** Status **/
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u32 rx_vect2_valid : 1;
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u32 resp_frame : 1;
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/** Decryption Status */
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u32 decr_status : 3;
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u32 rx_fifo_oflow : 1;
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/** Frame Unsuccessful */
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u32 undef_err : 1;
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u32 phy_err : 1;
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u32 fcs_err : 1;
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u32 addr_mismatch : 1;
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u32 ga_frame : 1;
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u32 current_ac : 2;
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u32 frm_successful_rx : 1;
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/** Descriptor Done */
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u32 desc_done_rx : 1;
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/** Key Storage RAM Index */
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u32 key_sram_index : 10;
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/** Key Storage RAM Index Valid */
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u32 key_sram_v : 1;
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u32 type : 2;
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u32 subtype : 4;
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};
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struct hw_rxhdr {
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/** RX vector */
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struct hw_vect hwvect;
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/** PHY channel information 1 */
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u32 phy_band : 8;
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u32 phy_channel_type : 8;
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u32 phy_prim20_freq : 16;
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/** PHY channel information 2 */
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u32 phy_center1_freq : 16;
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u32 phy_center2_freq : 16;
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/** RX flags */
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u32 flags_is_amsdu : 1;
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u32 flags_is_80211_mpdu: 1;
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u32 flags_is_4addr : 1;
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u32 flags_new_peer : 1;
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u32 flags_user_prio : 3;
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u32 flags_rsvd0 : 1;
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u32 flags_vif_idx : 8; // 0xFF if invalid VIF index
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u32 flags_sta_idx : 8; // 0xFF if invalid STA index
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u32 flags_dst_idx : 8; // 0xFF if unknown destination STA
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/** Pattern indicating if the buffer is available for the driver */
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u32 pattern;
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u32 payl_offset;
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u32 reserved_pad[2];
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/*XXX wild buffer load for platform overwrite*/
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u32 wild[8];
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};
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struct sm_reason_code {
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uint16_t reason_code;
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const char *action;
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};
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extern const u8 legrates_lut[];
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int bl_txdatacfm(void *pthis, void *hostid);
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void bl_prim_tbtt_ind(void *pthis);
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void bl_sec_tbtt_ind(void *pthis);
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void bl_rx_handle_msg(struct bl_hw *bl_hw, struct ipc_e2a_msg *msg);
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void bl_rx_pkt_cb(uint8_t *pkt, int len);
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#endif /* _RWNX_RX_H_ */
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