mirror of
https://github.com/pine64/bl_iot_sdk.git
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108 lines
4.1 KiB
C
108 lines
4.1 KiB
C
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/*
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* Copyright (c) 2020 Bouffalolab.
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*
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* This file is part of
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* *** Bouffalolab Software Dev Kit ***
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* (see www.bouffalolab.com).
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef REG_ACCESS_H_
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#define REG_ACCESS_H_
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/*****************************************************************************
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* Addresses within RWNX_ADDR_CPU
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*****************************************************************************/
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#define RAM_LMAC_FW_ADDR 0x00000000
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/*****************************************************************************
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* Addresses within RWNX_ADDR_SYSTEM
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*****************************************************************************/
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/* Shard RAM */
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#define SHARED_RAM_START_ADDR 0x00000000
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/* IPC registers */
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#define IPC_REG_BASE_ADDR 0x00800000
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/* System Controller Registers */
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#define SYSCTRL_SIGNATURE_ADDR 0x00900000
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#define SYSCTRL_MISC_CNTL_ADDR 0x009000E0
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#define BOOTROM_ENABLE BIT(4)
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#define FPGA_B_RESET BIT(1)
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#define SOFT_RESET BIT(0)
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/* MAC platform */
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#define NXMAC_SW_SET_PROFILING_ADDR 0x00B08564
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#define NXMAC_SW_CLEAR_PROFILING_ADDR 0x00B08568
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/* Modem Status */
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#define MDM_HDMCONFIG_ADDR 0x00C00000
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/* Modem Config */
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#define MDM_MEMCLKCTRL0_ADDR 0x00C00848
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#define MDM_CLKGATEFCTRL0_ADDR 0x00C00874
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/* AGC (trident) */
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#define AGC_RWNXAGCCNTL_ADDR 0x00C02060
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/* LDPC RAM*/
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#define PHY_LDPC_RAM_ADDR 0x00C09000
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/* FCU (elma )*/
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#define FCU_RWNXFCAGCCNTL_ADDR 0x00C09034
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/* AGC RAM */
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#define PHY_AGC_UCODE_ADDR 0x00C0A000
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/* RIU */
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#define RIU_RWNXVERSION_ADDR 0x00C0B000
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#define RIU_RWNXDYNAMICCONFIG_ADDR 0x00C0B008
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#define RIU_AGCMEMBISTSTAT_ADDR 0x00C0B238
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#define RIU_AGCMEMSIGNATURESTAT_ADDR 0x00C0B23C
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#define RIU_RWNXAGCCNTL_ADDR 0x00C0B390
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/* FCU RAM */
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#define PHY_FCU_UCODE_ADDR 0x00C0E000
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/* */
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#define FPGAB_MPIF_SEL_ADDR 0x00C10030
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/*****************************************************************************
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* Macros for generated register files
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*****************************************************************************/
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/* Macros for IPC registers access (used in reg_ipc_app.h) */
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#define REG_IPC_APP_RD(env, INDEX) \
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(*(volatile u32*)((u8*)env + IPC_REG_BASE_ADDR + 4*(INDEX)))
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#define REG_IPC_APP_WR(env, INDEX, value) \
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(*(volatile u32*)((u8*)env + IPC_REG_BASE_ADDR + 4*(INDEX)) = value)
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/* Macro used in reg_mac_core.h */
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#define REG_PL_RD(addr) 0
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#define REG_PL_WR(addr, value)
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#endif /* REG_ACCESS_H_ */
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