mirror of
https://github.com/pine64/bl_iot_sdk.git
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277 lines
8.1 KiB
C
277 lines
8.1 KiB
C
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/*
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* Copyright (c) 2020 Bouffalolab.
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*
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* This file is part of
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* *** Bouffalolab Software Dev Kit ***
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* (see www.bouffalolab.com).
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HAL_DESC_H_
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#define _HAL_DESC_H_
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#include "lmac_types.h"
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#define NX_TX_MAX_RATES 4
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/* Rate and policy table */
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#define N_CCK 8
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#define N_OFDM 8
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#define N_HT (8 * 2 * 2 * 4)
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#define N_VHT (10 * 4 * 2 * 8)
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#define N_RATE (N_CCK + N_OFDM + N_HT + N_VHT)
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/* Values for bwTx */
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#define __CHBW_CBW20 0
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#define __CHBW_CBW40 1
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#define __CHBW_CBW80 2
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#define __CHBW_CBW160 3
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/* Values for formatModTx */
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#define FORMATMOD_NON_HT 0
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#define FORMATMOD_NON_HT_DUP_OFDM 1
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#define FORMATMOD_HT_MF 2
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#define FORMATMOD_HT_GF 3
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#define FORMATMOD_VHT 4
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/* Values for navProtFrmEx */
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#define NAV_PROT_NO_PROT_BIT 0
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#define NAV_PROT_SELF_CTS_BIT 1
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#define NAV_PROT_RTS_CTS_BIT 2
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#define NAV_PROT_RTS_CTS_WITH_QAP_BIT 3
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#define NAV_PROT_STBC_BIT 4
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union bl_mcs_index {
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struct {
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u32 mcs : 3;
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u32 nss : 2;
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} ht;
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struct {
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u32 mcs : 4;
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u32 nss : 3;
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} vht;
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u32 legacy : 7;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union bl_rate_ctrl_info {
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struct {
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u32 mcsIndexTx : 7;
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u32 bwTx : 2;
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u32 shortGITx : 1;
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u32 preTypeTx : 1;
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u32 formatModTx : 3;
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u32 navProtFrmEx : 3;
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u32 mcsIndexProtTx : 7;
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u32 bwProtTx : 2;
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u32 formatModProtTx : 3;
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u32 nRetry : 3;
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};
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u32 value;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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struct bl_power_ctrl_info {
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u32 txPwrLevelPT : 8;
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u32 txPwrLevelProtPT : 8;
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u32 reserved :16;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union bl_pol_phy_ctrl_info_1 {
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struct {
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u32 rsvd1 : 3;
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u32 bfFrmEx : 1;
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u32 numExtnSS : 2;
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u32 fecCoding : 1;
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u32 stbc : 2;
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u32 rsvd2 : 5;
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u32 nTx : 3;
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u32 nTxProt : 3;
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};
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u32 value;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union bl_pol_phy_ctrl_info_2 {
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struct {
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u32 antennaSet : 8;
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u32 smmIndex : 8;
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u32 beamFormed : 1;
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};
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u32 value;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union bl_pol_mac_ctrl_info_1 {
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struct {
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u32 keySRamIndex : 10;
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u32 keySRamIndexRA : 10;
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};
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u32 value;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union bl_pol_mac_ctrl_info_2 {
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struct {
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u32 longRetryLimit : 8;
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u32 shortRetryLimit : 8;
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u32 rtsThreshold : 12;
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};
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u32 value;
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};
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#define POLICY_TABLE_PATTERN 0xBADCAB1E
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struct tx_policy_tbl {
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/* Unique Pattern at the start of Policy Table */
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u32 upatterntx;
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/* PHY Control 1 Information used by MAC HW */
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union bl_pol_phy_ctrl_info_1 phyctrlinfo_1;
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/* PHY Control 2 Information used by MAC HW */
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union bl_pol_phy_ctrl_info_2 phyctrlinfo_2;
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/* MAC Control 1 Information used by MAC HW */
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union bl_pol_mac_ctrl_info_1 macctrlinfo_1;
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/* MAC Control 2 Information used by MAC HW */
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union bl_pol_mac_ctrl_info_2 macctrlinfo_2;
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union bl_rate_ctrl_info ratectrlinfos[NX_TX_MAX_RATES];
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struct bl_power_ctrl_info powerctrlinfos[NX_TX_MAX_RATES];
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};
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/**
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* struct bl_hw_txstatus - Bitfield of confirmation status
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*
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* @tx_done: packet has been sucessfully transmitted
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* @retry_required: packet has been transmitted but not acknoledged.
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* Driver must repush it.
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* @sw_retry_required: packet has not been transmitted (FW wasn't able to push
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* it when it received it: not active channel ...). Driver must repush it.
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*/
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union bl_hw_txstatus {
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struct {
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u32 tx_done : 1;
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u32 retry_required : 1;
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u32 sw_retry_required : 1;
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u32 reserved :29;
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};
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u32 value;
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};
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/* Modem */
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#define MDM_PHY_CONFIG_TRIDENT 0
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#define MDM_PHY_CONFIG_ELMA 1
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#define MDM_PHY_CONFIG_KARST 2
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// MODEM features (from reg_mdm_stat.h)
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/// MUMIMOTX field bit
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#define MDM_MUMIMOTX_BIT ((u32)0x80000000)
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/// MUMIMOTX field position
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#define MDM_MUMIMOTX_POS 31
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/// MUMIMORX field bit
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#define MDM_MUMIMORX_BIT ((u32)0x40000000)
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/// MUMIMORX field position
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#define MDM_MUMIMORX_POS 30
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/// BFMER field bit
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#define MDM_BFMER_BIT ((u32)0x20000000)
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/// BFMER field position
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#define MDM_BFMER_POS 29
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/// BFMEE field bit
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#define MDM_BFMEE_BIT ((u32)0x10000000)
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/// BFMEE field position
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#define MDM_BFMEE_POS 28
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/// LDPCDEC field bit
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#define MDM_LDPCDEC_BIT ((u32)0x08000000)
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/// LDPCDEC field position
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#define MDM_LDPCDEC_POS 27
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/// LDPCENC field bit
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#define MDM_LDPCENC_BIT ((u32)0x04000000)
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/// LDPCENC field position
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#define MDM_LDPCENC_POS 26
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/// CHBW field mask
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#define MDM_CHBW_MASK ((u32)0x03000000)
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/// CHBW field LSB position
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#define MDM_CHBW_LSB 24
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/// CHBW field width
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#define MDM_CHBW_WIDTH ((u32)0x00000002)
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/// DSSSCCK field bit
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#define MDM_DSSSCCK_BIT ((u32)0x00800000)
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/// DSSSCCK field position
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#define MDM_DSSSCCK_POS 23
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/// NESS field mask
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#define MDM_NESS_MASK ((u32)0x00700000)
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/// NESS field LSB position
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#define MDM_NESS_LSB 20
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/// NESS field width
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#define MDM_NESS_WIDTH ((u32)0x00000003)
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/// RFMODE field mask
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#define MDM_RFMODE_MASK ((u32)0x000F0000)
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/// RFMODE field LSB position
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#define MDM_RFMODE_LSB 16
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/// RFMODE field width
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#define MDM_RFMODE_WIDTH ((u32)0x00000004)
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/// NSTS field mask
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#define MDM_NSTS_MASK ((u32)0x0000F000)
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/// NSTS field LSB position
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#define MDM_NSTS_LSB 12
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/// NSTS field width
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#define MDM_NSTS_WIDTH ((u32)0x00000004)
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/// NSS field mask
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#define MDM_NSS_MASK ((u32)0x00000F00)
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/// NSS field LSB position
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#define MDM_NSS_LSB 8
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/// NSS field width
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#define MDM_NSS_WIDTH ((u32)0x00000004)
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/// NTX field mask
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#define MDM_NTX_MASK ((u32)0x000000F0)
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/// NTX field LSB position
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#define MDM_NTX_LSB 4
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/// NTX field width
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#define MDM_NTX_WIDTH ((u32)0x00000004)
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/// NRX field mask
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#define MDM_NRX_MASK ((u32)0x0000000F)
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/// NRX field LSB position
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#define MDM_NRX_LSB 0
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/// NRX field width
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#define MDM_NRX_WIDTH ((u32)0x00000004)
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#define __MDM_PHYCFG_FROM_VERS(v) (((v) & MDM_RFMODE_MASK) >> MDM_RFMODE_LSB)
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#define RIU_FCU_PRESENT_MASK ((u32)0xFF000000)
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#define RIU_FCU_PRESENT_LSB 24
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#define __RIU_FCU_PRESENT(v) (((v) & RIU_FCU_PRESENT_MASK) >> RIU_FCU_PRESENT_LSB == 5)
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/// AGC load version field mask
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#define RIU_AGC_LOAD_MASK ((u32)0x00C00000)
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/// AGC load version field LSB position
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#define RIU_AGC_LOAD_LSB 22
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#define __RIU_AGCLOAD_FROM_VERS(v) (((v) & RIU_AGC_LOAD_MASK) >> RIU_AGC_LOAD_LSB)
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#endif // _HAL_DESC_H_
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