mirror of
https://github.com/pine64/bl_iot_sdk.git
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459 lines
13 KiB
C
459 lines
13 KiB
C
/*
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* Copyright (c) 2020 Bouffalolab.
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*
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* This file is part of
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* *** Bouffalolab Software Dev Kit ***
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* (see www.bouffalolab.com).
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <bl602_dma.h>
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#include <FreeRTOS.h>
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#include <task.h>
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#include "bl_dma.h"
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#include "bl_irq.h"
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#include <blog.h>
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#define DMA_CHANNEL_OFFSET 0x100
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#define DMA_Get_Channel(ch) (DMA_BASE+DMA_CHANNEL_OFFSET+(ch)*0x100)
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/*please also change NVIC_SetPriority of DMA channel*/
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#define DMA_DEFAULT_CHANNEL_COPY (DMA_CH0)
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#define MEM_UNIT_SIZE 1024
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#define DTCM_ADDR_START 0X2014000
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#define DTCM_ADDR_END (DTCM_ADDR_START + (48 * 1024))
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struct dma_ctx {
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utils_dlist_t *pstqueue;
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};
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struct dma_node {
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utils_dlist_t dlist_item;
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int channel;
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void *tc_handler;
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void *interr_handler;
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void *ctx;
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};
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static struct utils_list dma_copy_list;
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int bl_dma_int_clear(int ch)
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{
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uint32_t tmpVal;
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uint32_t intClr;
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/* Get DMA register */
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uint32_t DMAChs = DMA_BASE;
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tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
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if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) {
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/* Clear interrupt */
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tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
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intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
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intClr |= (1 << ch);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
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BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
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}
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tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
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if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) {
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/*Clear interrupt */
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tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
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intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
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intClr |= (1 << ch);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
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BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
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}
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return 0;
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}
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void bl_dma_update_memsrc(uint8_t ch, uint32_t src, uint32_t len)
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{
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uint32_t tmpVal;
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/* Get channel register */
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uint32_t DMAChs = DMA_Get_Channel(ch);
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/* Check the parameters */
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CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
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/* config channel config*/
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BL_WR_REG(DMAChs, DMA_SRCADDR, src);
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tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);
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BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
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}
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void bl_dma_update_memdst(uint8_t ch, uint32_t dst, uint32_t len)
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{
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uint32_t tmpVal;
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/* Get channel register */
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uint32_t DMAChs = DMA_Get_Channel(ch);
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/* Check the parameters */
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CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
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/* config channel config*/
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BL_WR_REG(DMAChs, DMA_DSTADDR, dst);
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tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);
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BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
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}
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static void inline _dma_copy_trigger(struct bl_dma_item *first)
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{
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//blog_info("------ DMA Trigger\r\n");
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DMA_LLI_Update(DMA_DEFAULT_CHANNEL_COPY, (uint32_t)&(first->src));
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DMA_Channel_Enable(DMA_DEFAULT_CHANNEL_COPY);
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}
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void bl_dma_copy(struct bl_dma_item *first)
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{
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taskENTER_CRITICAL();
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if (utils_list_is_empty(&dma_copy_list)) {
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_dma_copy_trigger(first);
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}
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utils_list_push_back(&dma_copy_list, &(first->item));
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taskEXIT_CRITICAL();
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}
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void bl_dma_IRQHandler(void)
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{
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struct bl_dma_item *first;
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//blog_info("------ Clear DMA now\r\n");
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bl_dma_int_clear(DMA_DEFAULT_CHANNEL_COPY);
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first = (struct bl_dma_item*)utils_list_pop_front(&dma_copy_list);
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if (NULL == first) {
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blog_info("[INT] ASSERT here for empty chain\r\n");
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while (1) {
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}
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}
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if (first->cb) {
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first->cb(first->arg);
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}
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/*prepare NEXT Transfer*/
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first = (struct bl_dma_item*)utils_list_pick(&dma_copy_list);
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if (first) {
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_dma_copy_trigger(first);
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}
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}
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void *bl_dma_mem_malloc(uint32_t size)
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{
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void *ptr;
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uint32_t counts, piece, ptr_piece_num;
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uint32_t *p_heap_addr;
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uint32_t addr_start, addr_end;
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addr_start = DTCM_ADDR_START;
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addr_end = DTCM_ADDR_END;
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ptr_piece_num = xPortGetFreeHeapSize() / MEM_UNIT_SIZE + 1;
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p_heap_addr = pvPortMalloc(ptr_piece_num * 4);
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memset(p_heap_addr, 0, ptr_piece_num * 4);
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if (p_heap_addr == NULL) {
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return NULL;
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}
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ptr = NULL;
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counts = 0;
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while (1) {
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ptr = pvPortMalloc(MEM_UNIT_SIZE);
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if (ptr == NULL) {
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goto __exit;
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}
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p_heap_addr[counts++] = (uint32_t)ptr;
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if ((uint32_t)((uint32_t)ptr & 0x0fffffff) >= addr_start) {
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if ((uint32_t)((uint32_t)ptr & 0x0fffffff) <= addr_end) {
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ptr = pvPortMalloc(size);
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break;
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}
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}
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}
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for (piece = 0; piece < counts; piece++) {
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vPortFree((uint32_t *)p_heap_addr[piece]);
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}
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__exit:
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vPortFree(p_heap_addr);
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return ptr;
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}
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void bl_dma_mem_free(void *ptr)
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{
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vPortFree(ptr);
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}
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static void bl_dma_int_process(void)
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{
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int ch;
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uint32_t intclr;
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uint32_t tmpval;
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uint32_t interr_val;
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struct dma_node *node;
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struct dma_ctx *pstctx;
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void (*handler)(void) = NULL;
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int tc_flag, interr_flag;
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tmpval = BL_RD_REG(DMA_BASE, DMA_INTTCSTATUS);
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interr_val = BL_RD_REG(DMA_BASE, DMA_INTERRORSTATUS);
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bl_irq_ctx_get(DMA_ALL_IRQn, (void **)&pstctx);
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for (ch = 0; ch < DMA_CH_MAX; ch++) {
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tc_flag = BL_GET_REG_BITS_VAL(tmpval, DMA_INTTCSTATUS) & (1 << ch);
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interr_flag = BL_GET_REG_BITS_VAL(interr_val, DMA_INTERRORSTATUS) & (1 << ch);
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if((tc_flag != 0) || (interr_flag != 0)) {
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if (tc_flag != 0) {
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/* tc int, clear interrupt */
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tmpval = BL_RD_REG(DMA_BASE, DMA_INTTCCLEAR);
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intclr = BL_GET_REG_BITS_VAL(tmpval, DMA_INTTCCLEAR);
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intclr |= (1 << ch);
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tmpval = BL_SET_REG_BITS_VAL(tmpval, DMA_INTTCCLEAR, intclr);
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BL_WR_REG(DMA_BASE, DMA_INTTCCLEAR, tmpval);
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}
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if (interr_flag != 0) {
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/* int error, clear interrupt */
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tmpval = BL_RD_REG(DMA_BASE, DMA_INTERRCLR);
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intclr = BL_GET_REG_BITS_VAL(tmpval, DMA_INTERRCLR);
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intclr |= (1 << ch);
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tmpval = BL_SET_REG_BITS_VAL(tmpval, DMA_INTERRCLR, intclr);
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BL_WR_REG(DMA_BASE, DMA_INTERRCLR, tmpval);
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}
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utils_dlist_for_each_entry(pstctx->pstqueue, node, struct dma_node, dlist_item) {
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if (ch == node->channel) {
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if (node->tc_handler != NULL && tc_flag != 0) {
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handler = (void(*)(void))node->tc_handler;
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handler();
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}
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if (node->interr_handler != NULL && interr_flag != 0) {
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handler = (void(*)(void))node->interr_handler;
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handler();
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}
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}
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}
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}
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}
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return;
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}
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int bl_dma_irq_register(int channel, void *tc_handler, void *interr_handler, void *ctx)
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{
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struct dma_ctx *pstctx;
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struct dma_node *node;
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struct dma_node *pstnode;
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if ((channel > DMA_CH_MAX || channel < 0) || tc_handler == NULL) {
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blog_error("not valid para \r\n");
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return -1;
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}
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bl_irq_ctx_get(DMA_ALL_IRQn, (void **)&pstctx);
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utils_dlist_for_each_entry(pstctx->pstqueue, node, struct dma_node, dlist_item) {
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if (channel == node->channel) {
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blog_warn("channel %d already register \r\n", node->channel);
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return -1;
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}
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}
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pstnode = pvPortMalloc(sizeof(struct dma_node));
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if (pstnode == NULL) {
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blog_error("malloc dma node failed. \r\n");
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}
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pstnode->channel = channel;
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pstnode->tc_handler = tc_handler;
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pstnode->interr_handler = interr_handler;
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pstnode->ctx = ctx;
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utils_dlist_add(&(pstnode->dlist_item), pstctx->pstqueue);
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return -1;
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}
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void *bl_dma_find_node_by_channel(int channel)
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{
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struct dma_ctx *pstctx;
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struct dma_node *node;
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bl_irq_ctx_get(DMA_ALL_IRQn, (void **)&pstctx);
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utils_dlist_for_each_entry(pstctx->pstqueue, node, struct dma_node, dlist_item) {
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if (node->channel == channel) {
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break;
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}
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}
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if (&(node->dlist_item) == pstctx->pstqueue) {
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blog_error("not find channel register. \r\n");
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return NULL;
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}
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return node;
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}
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void *bl_dma_find_ctx_by_channel(int channel)
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{
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struct dma_node *node;
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void *ctx;
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node = bl_dma_find_node_by_channel(channel);
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ctx = node->ctx;
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return ctx;
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}
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int bl_dma_irq_unregister(int channel)
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{
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struct dma_ctx *pstctx;
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struct dma_node *node;
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if (channel > DMA_CH_MAX || channel < 0) {
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blog_error("not valid para \r\n");
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return -1;
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}
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bl_irq_ctx_get(DMA_ALL_IRQn, (void **)&pstctx);
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utils_dlist_for_each_entry(pstctx->pstqueue, node, struct dma_node, dlist_item) {
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if (channel == node->channel) {
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utils_dlist_del(&(node->dlist_item));
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vPortFree(node);
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break;
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}
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}
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if (&node->dlist_item == pstctx->pstqueue) {
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blog_error("not find node \r\n");
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return -1;
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}
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return 0;
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}
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void bl_dma_init(void)
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{
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struct dma_ctx *pstctx;
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//FIXME use DMA_CH4 as channel copy
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DMA_Chan_Type dmaCh = DMA_DEFAULT_CHANNEL_COPY;
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DMA_LLI_Cfg_Type lliCfg =
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{
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DMA_TRNS_M2M,
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DMA_REQ_NONE,
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DMA_REQ_NONE,
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};
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utils_list_init(&dma_copy_list);
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pstctx = pvPortMalloc(sizeof(struct dma_ctx));
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if (pstctx == NULL) {
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blog_error("malloc dma ctx failed \r\n");
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return;
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}
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pstctx->pstqueue = pvPortMalloc(sizeof(utils_dlist_t));
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if (pstctx->pstqueue == NULL) {
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blog_error("malloc dma pstqueue failed \r\n");
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return;
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}
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INIT_UTILS_DLIST_HEAD(pstctx->pstqueue);
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DMA_Enable();
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DMA_IntMask(dmaCh, DMA_INT_ALL, MASK);
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DMA_IntMask(dmaCh, DMA_INT_TCOMPLETED, UNMASK);
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DMA_IntMask(dmaCh, DMA_INT_ERR, UNMASK);
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DMA_LLI_Init(dmaCh, &lliCfg);
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bl_irq_register_with_ctx(DMA_ALL_IRQn, bl_dma_int_process, pstctx);
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bl_dma_irq_register(DMA_DEFAULT_CHANNEL_COPY, bl_dma_IRQHandler, NULL, NULL);
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bl_irq_enable(DMA_ALL_IRQn);
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}
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static void _cb_cmd(void *arg)
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{
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struct bl_dma_item *first;
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first = (struct bl_dma_item*)arg;
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blog_info("[DMA] [TEST] Callback is working, arg is %p\r\n", arg);
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first->arg = NULL;
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}
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static void _dma_test_case1(void)
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{
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struct bl_dma_item *first;
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uint32_t *src;
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uint32_t *dst;
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const int size = 68;
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first = pvPortMalloc(sizeof(struct bl_dma_item));
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src = pvPortMalloc(size);
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dst = pvPortMalloc(size);
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blog_info("[TEST] [DMA] first %p, src %p, dst %p\r\n",
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first,
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src,
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dst
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);
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memset(first, 0, sizeof(struct bl_dma_item));
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memset(src, 1, size);
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memset(dst, 0xFF, size);
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first->src = (uint32_t)src;
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first->dst = (uint32_t)dst;
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first->next = 0;
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first->ctrl = BL_DMA_ITEM_CTRL_MAGIC_IRQ | (size >> 2);
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first->cb = _cb_cmd;
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first->arg = first;
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bl_dma_copy(first);
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/*Arg will be set in callback*/
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while (first->arg) {
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vTaskDelay(2);
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}
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vPortFree((void*)first->src);
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vPortFree((void*)first->dst);
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vPortFree(first);
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}
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void bl_dma_test(void)
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{
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_dma_test_case1();
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}
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