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Remove trailing whitespaces from bl602

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This commit is contained in:
Ferenc- 2020-11-05 10:21:53 +01:00
parent c84915a06c
commit 87d912e072
60 changed files with 1034 additions and 1034 deletions
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16
components/bl602/bl602/evb/src/debug.c
View File

@ -222,10 +222,10 @@ static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int
arg = modf(arg, &fi);
p1 = &buf[CVTBUFSIZE];
if (fi != 0)
if (fi != 0)
{
p1 = &buf[CVTBUFSIZE];
while (fi != 0)
while (fi != 0)
{
fj = modf(fi / 10, &fi);
*--p1 = (int)((fj + 0.03) * 10) + '0';
@ -235,7 +235,7 @@ static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int
}
else if (arg > 0)
{
while ((fj = arg * 10) < 1)
while ((fj = arg * 10) < 1)
{
arg = fj;
r2--;
@ -244,7 +244,7 @@ static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int
p1 = &buf[ndigits];
if (eflag == 0) p1 += r2;
*decpt = r2;
if (p1 < &buf[0])
if (p1 < &buf[0])
{
buf[0] = '\0';
return buf;
@ -255,7 +255,7 @@ static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int
arg = modf(arg, &fj);
*p++ = (int) fj + '0';
}
if (p1 >= &buf[CVTBUFSIZE])
if (p1 >= &buf[CVTBUFSIZE])
{
buf[CVTBUFSIZE - 1] = '\0';
return buf;
@ -292,8 +292,8 @@ char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)
return cvt(arg, ndigits, decpt, sign, buf, 0);
}
static void ee_bufcpy(char *d, char *s, int count);
static void ee_bufcpy(char *d, char *s, int count);
void ee_bufcpy(char *pd, char *ps, int count) {
char *pe=ps+count;
while (ps!=pe)
@ -415,7 +415,7 @@ static void decimal_point(char *buffer)
if (*buffer)
{
int n = strnlen(buffer,256);
while (n > 0)
while (n > 0)
{
buffer[n + 1] = buffer[n];
n--;

2
components/bl602/bl602_std/bl602_std/Common/cipher_suite/inc/bflb_hash.h
View File

@ -21,7 +21,7 @@
#define BFLB_HASH_TYPE_SHA256 2
#define BFLB_HASH_TYPE_SHA384 3
#define BFLB_HASH_TYPE_SHA512 4
typedef struct tag_bflb_hash_handle_t
{
bflb_hash_ctx_t hash_ctx;

4
components/bl602/bl602_std/bl602_std/Common/cipher_suite/inc/bflb_rsa.h
View File

@ -27,7 +27,7 @@ enum BFLB_RSA_PARA
BFLB_RSA_PARA_DQ,
BFLB_RSA_PARA_QP,
};
typedef struct tag_bflb_rsa_handle_t
{
bflb_rsa_ctx_t rsa_ctx;
@ -41,7 +41,7 @@ int32_t bflb_rsa_sign( bflb_rsa_handle_t *rsa_handle,const uint8_t *hash,
uint8_t hashlen,uint8_t hashtype,uint8_t *sig,uint32_t *slen);
int32_t bflb_rsa_verify( bflb_rsa_handle_t *rsa_handle,const uint8_t *hash,
uint8_t hashlen,uint8_t hashtype,const uint8_t *sig,uint32_t slen);
int32_t bflb_rsa_deinit( bflb_rsa_handle_t *rsa_handle);
#endif

14
components/bl602/bl602_std/bl602_std/Common/cipher_suite/src/bflb_crypt.c
View File

@ -432,7 +432,7 @@ int32_t bflb_crypt_deinit_do(bflb_crypt_handle_t *crypt_handle)
int32_t bflb_crypt_init(bflb_crypt_handle_t *crypt_handle,uint8_t type)
{
int32_t result = bflb_crypt_init_do(crypt_handle,type);
if(result==BFLB_CRYPT_OK){
crypt_handle->crypt_cfg.type=type;
}
@ -491,7 +491,7 @@ int32_t bflb_crypt_encrypt_tag(bflb_crypt_handle_t *crypt_handle,const uint8_t *
uint8_t *tag,uint8_t tag_len)
{
int32_t result;
result= bflb_crypt_encrypt_tag_do(crypt_handle,in,in_len,add,add_len,offset,out,tag,tag_len);
if( result != BFLB_CRYPT_OK)
@ -524,7 +524,7 @@ int32_t bflb_crypt_decrypt(bflb_crypt_handle_t *crypt_handle,const uint8_t *in,u
size_t offset,uint8_t *out)
{
int32_t result;
result=bflb_crypt_decrypt_do(crypt_handle,in,len,offset,out);
if( result != BFLB_CRYPT_OK)
@ -541,9 +541,9 @@ int32_t bflb_crypt_auth_decrypt(bflb_crypt_handle_t *crypt_handle,const uint8_t
const uint8_t *tag,uint8_t tag_len)
{
int32_t result;
result= bflb_crypt_auth_decrypt_do(crypt_handle,in,in_len,add,add_len,offset,out,tag,tag_len);
if( result != BFLB_CRYPT_OK)
{
bflb_crypt_printe("crypt auth and decrypt fail\r\n");
@ -556,9 +556,9 @@ int32_t bflb_crypt_auth_decrypt(bflb_crypt_handle_t *crypt_handle,const uint8_t
int32_t bflb_crypt_finish(bflb_crypt_handle_t *crypt_handle,uint8_t *tag,uint32_t len)
{
int32_t result;
result=bflb_crypt_finish_do(crypt_handle,tag,len);
if( result != BFLB_CRYPT_OK)
{
bflb_crypt_printe("crypt finish fail\r\n");

40
components/bl602/bl602_std/bl602_std/Common/cipher_suite/src/bflb_ecdsa.c
View File

@ -249,7 +249,7 @@ void bflb_ecdsa_point_add(uint8_t id)
//2*V^2
//PKA_MMUL(0,3,18,3, 9,3, 3,3,0);
Sec_Eng_PKA_MMUL(3,18,3,9,3,3,3,0,0);
//2*V^2*V2
//PKA_MMUL(0,3,18,3,18,3,16,3,0);
Sec_Eng_PKA_MMUL(3,18,3,18,3,16,3,0,0);
@ -315,79 +315,79 @@ void bflb_ecdsa_point_double(uint8_t id)
//X1^2-Z1^2
//PKA_MSUB(0,3,13,3,13,3,14,3,0);
Sec_Eng_PKA_MSUB(3,13,3,13,3,14,3,0,0);
//W = 3*(X1^2-Z1^2)
//PKA_MMUL(0,3,13,3,10,3,13,3,0);
Sec_Eng_PKA_MMUL(3,13,3,10,3,13,3,0,0);
//S = Y1*Z1
//PKA_MMUL(0,3,14,3, 6,3, 7,3,0);
Sec_Eng_PKA_MMUL(3,14,3,6,3,7,3,0,0);
//X1*Y1
//PKA_MMUL(0,3,15,3, 5,3, 6,3,0);
Sec_Eng_PKA_MMUL(3,15,3,5,3,6,3,0,0);
//W^2
//PKA_MMUL(0,3, 7,3,13,3,13,3,0);
Sec_Eng_PKA_MMUL(3,7,3,13,3,13,3,0,0);
//B = X1*Y1*S
//PKA_MMUL(0,3,15,3,15,3,14,3,0);
Sec_Eng_PKA_MMUL(3,15,3,15,3,14,3,0,0);
//8*B
//PKA_MMUL(0,3, 5,3,12,3,15,3,0);
Sec_Eng_PKA_MMUL(3,5,3,12,3,15,3,0,0);
//H = W^2-8*B
//PKA_MSUB(0,3, 7,3, 7,3, 5,3,0);
Sec_Eng_PKA_MSUB(3,7,3,7,3,5,3,0,0);
//2*H
//PKA_MMUL(0,3, 5,3, 9,3, 7,3,0);
Sec_Eng_PKA_MMUL(3, 5,3,9,3,7,3,0,0);
//X2 = 2*H*S
//PKA_MMUL(0,3, 5,3, 5,3,14,3,0);
Sec_Eng_PKA_MMUL(3, 5,3,5,3,14,3,0,0);
//4*B
//PKA_MMUL(0,3,15,3,11,3,15,3,0);
Sec_Eng_PKA_MMUL(3,15,3,11,3,15,3,0,0);
//S^2
//PKA_MMUL(0,3,16,3,14,3,14,3,0);
Sec_Eng_PKA_MMUL(3,16,3,14,3,14,3,0,0);
//4*B-H
//PKA_MSUB(0,3,15,3,15,3, 7,3,0);
Sec_Eng_PKA_MSUB(3,15,3,15,3,7,3,0,0);
//Y1^2
//PKA_MMUL(0,3, 6,3, 6,3, 6,3,0);
Sec_Eng_PKA_MMUL(3,6,3,6,3,6,3,0,0);
//W*(4*B-H)
//PKA_MMUL(0,3,15,3,15,3,13,3,0);
Sec_Eng_PKA_MMUL(3,15,3,15,3,13,3,0,0);
//8*Y1^2
//PKA_MMUL(0,3, 6,3,12,3, 6,3,0);
Sec_Eng_PKA_MMUL(3,6,3,12,3,6,3,0,0);
//8*Y1^2*S^2
//PKA_MMUL(0,3, 6,3, 6,3,16,3,0);
Sec_Eng_PKA_MMUL(3,6,3,6,3,16,3,0,0);
//Y2 = W*(4*B-H)-8*Y1^2*S^2
//PKA_MSUB(0,3, 6,3,15,3, 6,3,0);
Sec_Eng_PKA_MSUB(3,6,3,15,3,6,3,0,0);
//S^3
//PKA_MMUL(0,3, 7,3,14,3,16,3,0);
Sec_Eng_PKA_MMUL(3,7,3,14,3,16,3,0,0);
//Z2 = 8*S^3
//PKA_MMUL(1,3, 7,3,12,3, 7,3,0);
Sec_Eng_PKA_MMUL(3,7,3,12,3,7,3,0,1);

12
components/bl602/bl602_std/bl602_std/Common/cipher_suite/src/bflb_hash.c
View File

@ -52,7 +52,7 @@ int32_t bflb_hash_init(bflb_hash_handle_t *hash_handle,uint8_t type)
bflb_hash_printe("unsupported type\r\n");
ret=BFLB_HASH_ERROR;
break;
}
if(ret==BFLB_HASH_OK){
hash_handle->type=type;
@ -65,7 +65,7 @@ int32_t bflb_hash_start(bflb_hash_handle_t *hash_handle)
int32_t ret = BFLB_HASH_OK;
switch(hash_handle->type)
{
case BFLB_HASH_TYPE_SHA1:
@ -83,7 +83,7 @@ int32_t bflb_hash_start(bflb_hash_handle_t *hash_handle)
default:
bflb_hash_printe("unsupported type\r\n");
return BFLB_HASH_ERROR;
}
if(ret!=0){
bflb_hash_printe("hash start fail\r\n");
@ -113,7 +113,7 @@ int32_t bflb_hash_update(bflb_hash_handle_t *hash_handle,const uint8_t *in,uint3
default:
bflb_hash_printe("unsupported type\r\n");
return BFLB_HASH_ERROR;
}
if(ret!=0){
bflb_hash_printe("hash update fail\r\n");
@ -144,7 +144,7 @@ int32_t bflb_hash_finish(bflb_hash_handle_t *hash_handle,uint8_t *out)
default:
bflb_hash_printe("unsupported type\r\n");
return BFLB_HASH_ERROR;
}
if(ret!=0){
bflb_hash_printe("hash finish fail\r\n");
@ -171,7 +171,7 @@ int32_t bflb_hash_deinit(bflb_hash_handle_t *hash_handle)
default:
bflb_hash_printe("unsupported type\r\n");
return BFLB_HASH_ERROR;
}
memset(hash_handle,0,sizeof(bflb_hash_handle_t));

28
components/bl602/bl602_std/bl602_std/Common/cipher_suite/src/bflb_rsa.c
View File

@ -14,7 +14,7 @@ int32_t bflb_rsa_set_parameter(bflb_rsa_handle_t *rsa_handle,int type,uint8_t *v
{
int32_t ret = BFLB_RSA_OK;
mbedtls_rsa_context* rsa=(mbedtls_rsa_context*)&rsa_handle->rsa_ctx;
switch(type)
{
case BFLB_RSA_PARA_N:
@ -46,7 +46,7 @@ int32_t bflb_rsa_set_parameter(bflb_rsa_handle_t *rsa_handle,int type,uint8_t *v
ret=BFLB_RSA_ERROR;
break;
}
return ret;
}
@ -54,7 +54,7 @@ int32_t bflb_rsa_check_private(bflb_rsa_handle_t *rsa_handle)
{
int32_t ret = BFLB_RSA_OK;
mbedtls_rsa_context* rsa=(mbedtls_rsa_context*)&rsa_handle->rsa_ctx;
if( ( ret = mbedtls_rsa_check_privkey( rsa ) ) != 0 )
{
bflb_rsa_printe("failed\r\n!rsa_check_privkey failed with -0x%0x\n", -ret );
@ -74,7 +74,7 @@ int32_t bflb_rsa_check_public(bflb_rsa_handle_t *rsa_handle)
bflb_rsa_printe("failed\r\n!rsa_check_privkey failed with -0x%0x\n", -ret );
return BFLB_RSA_ERROR;
}
return BFLB_RSA_OK;
}
@ -83,7 +83,7 @@ int32_t bflb_rsa_sign( bflb_rsa_handle_t *rsa_handle,const uint8_t *hash,
{
int32_t ret = BFLB_RSA_OK;
mbedtls_rsa_context* rsa=(mbedtls_rsa_context*)&rsa_handle->rsa_ctx;
ret = mbedtls_rsa_pkcs1_sign( rsa, NULL, NULL, MBEDTLS_RSA_PRIVATE,
(mbedtls_md_type_t)bflb_hash_get_type(hashtype),
hashlen, hash, sig );
@ -91,9 +91,9 @@ int32_t bflb_rsa_sign( bflb_rsa_handle_t *rsa_handle,const uint8_t *hash,
{
bflb_rsa_printe("failed\r\n!rsa_pkcs1_sign failed with -0x%0x\n", -ret );
return BFLB_RSA_ERROR;
}
}
*slen=rsa->len;
return BFLB_RSA_OK;
return BFLB_RSA_OK;
}
int32_t bflb_rsa_verify( bflb_rsa_handle_t *rsa_handle,const uint8_t *hash,
@ -101,24 +101,24 @@ int32_t bflb_rsa_verify( bflb_rsa_handle_t *rsa_handle,const uint8_t *hash,
{
int32_t ret = BFLB_RSA_OK;
mbedtls_rsa_context* rsa=(mbedtls_rsa_context*)&rsa_handle->rsa_ctx;
ret = mbedtls_rsa_pkcs1_verify( rsa, NULL, NULL, MBEDTLS_RSA_PUBLIC,
ret = mbedtls_rsa_pkcs1_verify( rsa, NULL, NULL, MBEDTLS_RSA_PUBLIC,
(mbedtls_md_type_t)bflb_hash_get_type(hashtype),
hashlen, hash, sig );
if( ret != 0 )
{
bflb_rsa_printe("failed\r\n!rsa_pkcs1_verify failed with -0x%0x\n", -ret );
return BFLB_RSA_ERROR;
}
return BFLB_RSA_OK;
}
return BFLB_RSA_OK;
}
int32_t bflb_rsa_deinit( bflb_rsa_handle_t *rsa_handle)
{
mbedtls_rsa_context* rsa=(mbedtls_rsa_context*)&rsa_handle->rsa_ctx;
mbedtls_rsa_free( rsa );
memset(rsa_handle,0,sizeof(bflb_rsa_handle_t));
return BFLB_RSA_OK;
return BFLB_RSA_OK;
}

12
components/bl602/bl602_std/bl602_std/Common/platform_print/platform_device.c
View File

@ -330,11 +330,11 @@ void bflb_platform_init(uint32_t baudrate)
return ;
}
init_flag = PLATFORM_INIT_TRUE;
bflb_platform_init_time();
Sec_Eng_Trng_Enable();
if(!uart_dbg_disable){
bflb_platform_uart_dbg_init(baudrate);
bflb_platform_printf("system clock=%dM\r\n",SystemCoreClockGet()/1000000);
@ -348,11 +348,11 @@ void bflb_platform_deinit()
return ;
}
init_flag = PLATFORM_INIT_FALSE;
bflb_platform_deinit_time();
Sec_Eng_Trng_Disable();
if(!uart_dbg_disable){
bflb_platform_uart_dbg_deinit();
}

104
components/bl602/bl602_std/bl602_std/Common/ring_buffer/ring_buffer.c
View File

@ -100,20 +100,20 @@ BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type* rbType,uint8_t* buffer,uint16_t s
{
/* Init ring buffer pointer */
rbType->pointer = buffer;
/* Init read/write mirror and index */
rbType->readMirror = 0;
rbType->readIndex = 0;
rbType->writeMirror = 0;
rbType->writeIndex = 0;
/* Set ring buffer size */
rbType->size = size;
/* Set lock and unlock callback function */
rbType->lock = lockCb;
rbType->unlock = unlockCb;
return SUCCESS;
}
@ -133,7 +133,7 @@ BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type* rbType)
rbType->readIndex = 0;
rbType->writeMirror = 0;
rbType->writeIndex = 0;
return SUCCESS;
}
@ -152,15 +152,15 @@ BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type* rbType)
uint16_t Ring_Buffer_Write_Callback(Ring_Buffer_Type* rbType,uint16_t length,ringBuffer_Write_Callback* writeCb,void* parameter)
{
uint16_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType);
if(writeCb == NULL){
return 0;
}
if(rbType->lock != NULL){
rbType->lock();
}
/* Ring buffer has no space for new data */
if(sizeRemained == 0){
if(rbType->unlock != NULL){
@ -168,15 +168,15 @@ uint16_t Ring_Buffer_Write_Callback(Ring_Buffer_Type* rbType,uint16_t length,rin
}
return 0;
}
/* Drop part of data when length out of space remained */
if(length > sizeRemained){
length = sizeRemained;
}
/* Get size of space remained in current mirror */
sizeRemained = rbType->size - rbType->writeIndex;
if(sizeRemained > length){
/* Space remained is enough for data in current mirror */
writeCb(parameter,&rbType->pointer[rbType->writeIndex],length);
@ -188,7 +188,7 @@ uint16_t Ring_Buffer_Write_Callback(Ring_Buffer_Type* rbType,uint16_t length,rin
rbType->writeIndex = length-sizeRemained;
rbType->writeMirror = ~rbType->writeMirror;
}
if(rbType->unlock != NULL){
rbType->unlock();
}
@ -209,7 +209,7 @@ uint16_t Ring_Buffer_Write_Callback(Ring_Buffer_Type* rbType,uint16_t length,rin
static void Ring_Buffer_Write_Copy(void* parameter,uint8_t* dest,uint16_t length)
{
uint8_t **src = (uint8_t **)parameter;
ARCH_MemCpy_Fast(dest,*src,length);
*src += length;
}
@ -245,7 +245,7 @@ uint16_t Ring_Buffer_Write_Byte(Ring_Buffer_Type* rbType,const uint8_t data)
if(rbType->lock != NULL){
rbType->lock();
}
/* Ring buffer has no space for new data */
if(!Ring_Buffer_Get_Empty_Length(rbType)){
if(rbType->unlock != NULL){
@ -253,9 +253,9 @@ uint16_t Ring_Buffer_Write_Byte(Ring_Buffer_Type* rbType,const uint8_t data)
}
return 0;
}
rbType->pointer[rbType->writeIndex] = data;
/* Judge to change index and mirror */
if(rbType->writeIndex != (rbType->size-1)){
rbType->writeIndex++;
@ -263,7 +263,7 @@ uint16_t Ring_Buffer_Write_Byte(Ring_Buffer_Type* rbType,const uint8_t data)
rbType->writeIndex = 0;
rbType->writeMirror = ~rbType->writeMirror;
}
if(rbType->unlock != NULL){
rbType->unlock();
}
@ -286,22 +286,22 @@ uint16_t Ring_Buffer_Write_Force(Ring_Buffer_Type* rbType,const uint8_t* data,ui
{
uint16_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType);
uint16_t indexRemained = rbType->size - rbType->writeIndex;
if(rbType->lock != NULL){
rbType->lock();
}
/* Drop extra data when data length is large than size of ring buffer */
if(length > rbType->size){
data = &data[length - rbType->size];
length = rbType->size;
}
if(indexRemained > length){
/* Space remained is enough for data in current mirror */
ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex],data,length);
rbType->writeIndex += length;
/* Update read index */
if(length > sizeRemained){
rbType->readIndex = rbType->writeIndex;
@ -312,14 +312,14 @@ uint16_t Ring_Buffer_Write_Force(Ring_Buffer_Type* rbType,const uint8_t* data,ui
ARCH_MemCpy_Fast(&rbType->pointer[0],&data[indexRemained],length-indexRemained);
rbType->writeIndex = length-indexRemained;
rbType->writeMirror = ~rbType->writeMirror;
/* Update read index and mirror */
if(length > sizeRemained){
rbType->readIndex = rbType->writeIndex;
rbType->readMirror = ~rbType->readMirror;
}
}
if(rbType->unlock != NULL){
rbType->unlock();
}
@ -340,18 +340,18 @@ uint16_t Ring_Buffer_Write_Force(Ring_Buffer_Type* rbType,const uint8_t* data,ui
uint16_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type* rbType,const uint8_t data)
{
Ring_Buffer_Status_Type status = Ring_Buffer_Get_Status(rbType);
if(rbType->lock != NULL){
rbType->lock();
}
rbType->pointer[rbType->writeIndex] = data;
/* Judge to change index and mirror */
if(rbType->writeIndex == rbType->size-1){
rbType->writeIndex = 0;
rbType->writeMirror = ~rbType->writeMirror;
/* Update read index and mirror */
if(status == RING_BUFFER_FULL){
rbType->readIndex = rbType->writeIndex;
@ -359,13 +359,13 @@ uint16_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type* rbType,const uint8_t dat
}
}else{
rbType->writeIndex++;
/* Update read index */
if(status == RING_BUFFER_FULL){
rbType->readIndex = rbType->writeIndex;
}
}
if(rbType->unlock != NULL){
rbType->unlock();
}
@ -387,15 +387,15 @@ uint16_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type* rbType,const uint8_t dat
uint16_t Ring_Buffer_Read_Callback(Ring_Buffer_Type* rbType,uint16_t length,ringBuffer_Read_Callback* readCb,void* parameter)
{
uint16_t size = Ring_Buffer_Get_Length(rbType);
if(readCb == NULL){
return 0;
}
if(rbType->lock != NULL){
rbType->lock();
}
/* Ring buffer has no data */
if(!size){
if(rbType->unlock != NULL){
@ -403,15 +403,15 @@ uint16_t Ring_Buffer_Read_Callback(Ring_Buffer_Type* rbType,uint16_t length,ring
}
return 0;
}
/* Ring buffer do not have enough data */
if(size < length){
length = size;
}
/* Get size of space remained in current mirror */
size = rbType->size - rbType->readIndex;
if(size > length){
/* Read all data needed */
readCb(parameter,&rbType->pointer[rbType->readIndex],length);
@ -423,7 +423,7 @@ uint16_t Ring_Buffer_Read_Callback(Ring_Buffer_Type* rbType,uint16_t length,ring
rbType->readIndex = length-size;
rbType->readMirror = ~rbType->readMirror;
}
if(rbType->unlock != NULL){
rbType->unlock();
}
@ -444,7 +444,7 @@ uint16_t Ring_Buffer_Read_Callback(Ring_Buffer_Type* rbType,uint16_t length,ring
static void Ring_Buffer_Read_Copy(void* parameter,uint8_t* data,uint16_t length)
{
uint8_t **dest = (uint8_t **)parameter;
ARCH_MemCpy_Fast(*dest,data,length);
*dest += length;
}
@ -480,7 +480,7 @@ uint16_t Ring_Buffer_Read_Byte(Ring_Buffer_Type* rbType,uint8_t* data)
if(rbType->lock != NULL){
rbType->lock();
}
/* Ring buffer has no data */
if(!Ring_Buffer_Get_Length(rbType)){
if(rbType->unlock != NULL){
@ -488,10 +488,10 @@ uint16_t Ring_Buffer_Read_Byte(Ring_Buffer_Type* rbType,uint8_t* data)
}
return 0;
}
/* Read data */
*data = rbType->pointer[rbType->readIndex];
/* Update read index and mirror */
if(rbType->readIndex == rbType->size-1){
rbType->readIndex = 0;
@ -499,7 +499,7 @@ uint16_t Ring_Buffer_Read_Byte(Ring_Buffer_Type* rbType,uint8_t* data)
}else{
rbType->readIndex++;
}
if(rbType->unlock != NULL){
rbType->unlock();
}
@ -520,11 +520,11 @@ uint16_t Ring_Buffer_Read_Byte(Ring_Buffer_Type* rbType,uint8_t* data)
uint16_t Ring_Buffer_Peek(Ring_Buffer_Type* rbType,uint8_t* data,uint16_t length)
{
uint16_t size = Ring_Buffer_Get_Length(rbType);
if(rbType->lock != NULL){
rbType->lock();
}
/* Ring buffer has no data */
if(!size){
if(rbType->unlock != NULL){
@ -532,15 +532,15 @@ uint16_t Ring_Buffer_Peek(Ring_Buffer_Type* rbType,uint8_t* data,uint16_t length
}
return 0;
}
/* Ring buffer do not have enough data */
if(size < length){
length = size;
}
/* Get size of space remained in current mirror */
size = rbType->size - rbType->readIndex;
if(size > length){
/* Read all data needed */
ARCH_MemCpy_Fast(data,&rbType->pointer[rbType->readIndex],length);
@ -549,7 +549,7 @@ uint16_t Ring_Buffer_Peek(Ring_Buffer_Type* rbType,uint8_t* data,uint16_t length
ARCH_MemCpy_Fast(data,&rbType->pointer[rbType->readIndex],size);
ARCH_MemCpy_Fast(&data[size],&rbType->pointer[0],length-size);
}
if(rbType->unlock != NULL){
rbType->unlock();
}
@ -571,7 +571,7 @@ uint16_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type* rbType,uint8_t* data)
if(rbType->lock != NULL){
rbType->lock();
}
/* Ring buffer has no data */
if(!Ring_Buffer_Get_Length(rbType)){
if(rbType->unlock != NULL){
@ -579,10 +579,10 @@ uint16_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type* rbType,uint8_t* data)
}
return 0;
}
/* Read data */
*data = rbType->pointer[rbType->readIndex];
if(rbType->unlock != NULL){
rbType->unlock();
}
@ -603,7 +603,7 @@ uint16_t Ring_Buffer_Get_Length(Ring_Buffer_Type* rbType)
if(rbType->lock != NULL){
rbType->lock();
}
if(rbType->readMirror == rbType->writeMirror){
if(rbType->unlock != NULL){
rbType->unlock();
@ -645,7 +645,7 @@ Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type* rbType)
if(rbType->lock != NULL){
rbType->lock();
}
/* Judge empty or full */
if(rbType->readIndex == rbType->writeIndex){
if(rbType->readMirror == rbType->writeMirror){

6
components/bl602/bl602_std/bl602_std/Common/sim_print/bflb_platform.h
View File

@ -11,7 +11,7 @@
#define WRITE_REG(a,v) *((volatile uint32_t *)(a))=(v)
#define MSG_PRINT_MSG_LEN (0x200)
#define SV_C_SHARE_LEN (0x200)
#define DBG_BASE (0x5201bc00)
#define DBG_BASE (0x5201bc00)
#define MSG_PRINT_MARK_ADR (DBG_BASE)
@ -29,10 +29,10 @@
extern void BL602_Delay_US(uint32_t cnt);
#define MSG(a,...) {sprintf((char*)MSG_PRINT_MSG_ADR, a, ##__VA_ARGS__);\
WRITE_REG(MSG_PRINT_MARK_ADR, MSG_PRINT_MSG_MARK);}
WRITE_REG(MSG_PRINT_MARK_ADR, MSG_PRINT_MSG_MARK);}
#define MSG_ERR(a,...) {sprintf((char*)MSG_PRINT_MSG_ADR, a, ##__VA_ARGS__); \
WRITE_REG(MSG_PRINT_MARK_ADR, MSG_PRINT_ERR_MSG_MARK);}
#define SIM_END WRITE_REG(SIM_END_MARK_ADR, SIM_END_MARK)
#define SIM_FAIL {MSG_ERR("sw sim fail"); SIM_END;}

16
components/bl602/bl602_std/bl602_std/Common/soft_crc/softcrc.c
View File

@ -9,9 +9,9 @@
// ---------------- POPULAR POLYNOMIALS ----------------
// CCITT: x^16 + x^12 + x^5 + x^0 (0x1021,init 0x0000)
// CRC-16: x^16 + x^15 + x^2 + x^0 (0x8005,init 0xFFFF)
// we use 0x8005 here and
// we use 0x8005 here and
const uint8_t chCRCHTalbe[] =
const uint8_t chCRCHTalbe[] =
{
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
@ -37,7 +37,7 @@ const uint8_t chCRCHTalbe[] =
0x00, 0xC1, 0x81, 0x40
};
const uint8_t chCRCLTalbe[] =
const uint8_t chCRCLTalbe[] =
{
0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
@ -65,9 +65,9 @@ const uint8_t chCRCLTalbe[] =
uint16_t BFLB_Soft_CRC16(void * dataIn, uint32_t len)
{
uint8_t chCRCHi = 0xFF;
uint8_t chCRCLo = 0xFF;
uint16_t wIndex;
uint8_t chCRCHi = 0xFF;
uint8_t chCRCLo = 0xFF;
uint16_t wIndex;
uint8_t* data=(uint8_t *) dataIn;
while (len--){
@ -132,7 +132,7 @@ uint32_t BFLB_Soft_CRC32_Table( void *dataIn, uint32_t len)
{
uint32_t crc=0;
uint8_t *data=(uint8_t *)dataIn;
crc = crc ^ 0xffffffff;
while (len--)
@ -157,7 +157,7 @@ uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len)
uint8_t i;
uint32_t crc = 0xffffffff; // Initial value
uint8_t *data=(uint8_t *)dataIn;
while(len--){
crc ^= *data++; // crc ^= *data; data++;
for (i = 0; i < 8; ++i){

4
components/bl602/bl602_std/bl602_std/Common/xz/xz_port.c
View File

@ -7,13 +7,13 @@ void simple_malloc_init(void)
malloced=0;
}
void * simple_malloc(uint32_t size)
{
{
uint8_t *p;
MSG_DBG("Simple Malloc %d\r\n",size);
if(malloced+size<sizeof(mallocBuf)){
p=mallocBuf+malloced;
malloced+=size;
return p;
return p;
}
return NULL;
}

2
components/bl602/bl602_std/bl602_std/RISCV/Core/Include/clic.h
View File

@ -18,4 +18,4 @@
#define CLIC_INTCFG 0x800
#define CLIC_CFG 0xc00
#endif /* _SIFIVE_CLIC_H */
#endif /* _SIFIVE_CLIC_H */

30
components/bl602/bl602_std/bl602_std/RISCV/Core/Include/riscv_encoding.h
View File

@ -99,15 +99,15 @@
#define MIP_HEIP (1 << IRQ_H_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)
#define MIE_SSIE MIP_SSIP
#define MIE_HSIE MIP_HSIP
#define MIE_MSIE MIP_MSIP
#define MIE_STIE MIP_STIP
#define MIE_HTIE MIP_HTIP
#define MIE_MTIE MIP_MTIP
#define MIE_SEIE MIP_SEIP
#define MIE_HEIE MIP_HEIP
#define MIE_MEIE MIP_MEIP
#define MIE_SSIE MIP_SSIP
#define MIE_HSIE MIP_HSIP
#define MIE_MSIE MIP_MSIP
#define MIE_STIE MIP_STIP
#define MIE_HTIE MIP_HTIP
#define MIE_MTIE MIP_MTIP
#define MIE_SEIE MIP_SEIP
#define MIE_HEIE MIP_HEIP
#define MIE_MEIE MIP_MEIP
#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP
@ -176,7 +176,7 @@
#ifdef __GNUC__
#define asm __asm
#define asm __asm
#define read_fpu(reg) ({ unsigned long __tmp; \
asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \
@ -187,7 +187,7 @@
asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \
else \
asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); })
#define read_csr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
@ -1136,28 +1136,28 @@ DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2,
DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2,
MASK_CUSTOM0_RD_RS1_RS2)
DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2,
DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2,
MASK_CUSTOM1_RD_RS1_RS2)
DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2,
DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2,
MASK_CUSTOM2_RD_RS1_RS2)
DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2,
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2,
MASK_CUSTOM3_RD_RS1_RS2)
#endif
#ifdef DECLARE_CSR

4
components/bl602/bl602_std/bl602_std/RISCV/Device/Bouffalo/BL602/Startup/GCC/start_load.c
View File

@ -39,7 +39,7 @@ extern uint32_t __HeapLimit;
void start_load(void) {
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
uint32_t *pTable __attribute__((unused));
/* Copy ITCM code */
pSrc = &__itcm_load_addr;
@ -82,5 +82,5 @@ void start_load(void) {
for ( ; pDest < &__bss_end__ ; ) {
*pDest++ = 0ul;
}
#endif
#endif
}

2
components/bl602/bl602_std/bl602_std/RISCV/Device/Bouffalo/BL602/Startup/system_bl602.c
View File

@ -48,7 +48,7 @@ void SystemInit (void)
.errEn=DISABLE,
.arbMod=L1C_BMX_ARB_FIX,
};
/* NP boot log Flag */
p= (uint32_t *)(BFLB_BOOTROM_NP_BOOT_LOG_ADDR);
*p=0x5A5AA5A5;

30
components/bl602/bl602_std/bl602_std/StdDriver/Inc/bl602_common.h
View File

@ -19,9 +19,9 @@
/**
* @brief Error type definition
*/
typedef enum
typedef enum
{
SUCCESS = 0,
SUCCESS = 0,
ERROR = 1,
TIMEOUT = 2,
}BL_Err_Type;
@ -29,27 +29,27 @@ typedef enum
/**
* @brief Functional type definition
*/
typedef enum
typedef enum
{
DISABLE = 0,
DISABLE = 0,
ENABLE = 1,
}BL_Fun_Type;
/**
* @brief Status type definition
*/
typedef enum
typedef enum
{
RESET = 0,
RESET = 0,
SET = 1,
}BL_Sts_Type;
/**
* @brief Mask type definition
*/
typedef enum
typedef enum
{
UNMASK = 0,
UNMASK = 0,
MASK = 1
}BL_Mask_Type;
@ -58,7 +58,7 @@ typedef enum
/** @defgroup COMMON_Public_Constants
* @{
*/
/** @defgroup DRIVER_INT_PERIPH
* @{
*/
@ -66,7 +66,7 @@ typedef enum
/*@} end of group DRIVER_INT_PERIPH */
/** @defgroup DRIVER_INT_MASK
/** @defgroup DRIVER_INT_MASK
* @{
*/
#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
@ -103,22 +103,22 @@ void check_failed(uint8_t *file, uint32_t line);
/**
* @brief Logical status Type definition
*/
typedef enum
typedef enum
{
LOGIC_LO = 0,
LOGIC_LO = 0,
LOGIC_HI = !LOGIC_LO
}LogicalStatus;
/**
* @brief Active status Type definition
*/
typedef enum
typedef enum
{
DEACTIVE = 0,
DEACTIVE = 0,
ACTIVE = !DEACTIVE
}ActiveStatus;
/**
/**
* @brief Interrupt callback function type
*/
typedef void (intCallback_Type)(void);

6
components/bl602/bl602_std/bl602_std/StdDriver/Inc/bl602_dma.h
View File

@ -160,9 +160,9 @@ typedef struct {
DMA_Chan_Type ch; /*!< Channel select 0-4 */
DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */
DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */
DMA_Burst_Size_Type srcBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
DMA_Burst_Size_Type srcBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */
DMA_Burst_Size_Type dstBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
DMA_Burst_Size_Type dstBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */
uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */
uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */
@ -209,7 +209,7 @@ typedef struct {
DMA_LLI_Cfg_Type *DMA_LLI_Cfg; /*!< LLI Config parameter */
uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */
uint32_t chache_buf_addr[2]; /*!< Ping-Pong structure chache */
BL_Fun_Type is_single_mode; /*!< is Ping-pong running forever or single mode ,if is single mode ping-pong will run only once
BL_Fun_Type is_single_mode; /*!< is Ping-pong running forever or single mode ,if is single mode ping-pong will run only once
after one start */
}DMA_LLI_PP_Struct;

22
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_acomp.c
View File

@ -96,16 +96,16 @@
void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo,AON_ACOMP_CFG_Type *cfg)
{
uint32_t tmpVal = 0;
/* Check the parameters */
CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
if(acompNo==AON_ACOMP0_ID){
/* Disable ACOMP first */
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP0_CTRL);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_ACOMP0_EN);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP0_CTRL,tmpVal);
/* Set ACOMP config */
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_MUXEN,cfg->muxEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_POS_SEL,cfg->posChanSel);
@ -114,15 +114,15 @@ void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo,AON_ACOMP_CFG_Type *cfg)
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_BIAS_PROG,cfg->biasProg);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_HYST_SELP,cfg->hysteresisPosVolt);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_HYST_SELN,cfg->hysteresisNegVolt);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP0_CTRL,tmpVal);
}else{
/* Disable ACOMP first */
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP1_CTRL);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_ACOMP1_EN);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP1_CTRL,tmpVal);
/* Set ACOMP config */
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_MUXEN,cfg->muxEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_POS_SEL,cfg->posChanSel);
@ -131,7 +131,7 @@ void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo,AON_ACOMP_CFG_Type *cfg)
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_BIAS_PROG,cfg->biasProg);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_HYST_SELP,cfg->hysteresisPosVolt);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_HYST_SELN,cfg->hysteresisNegVolt);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP1_CTRL,tmpVal);
}
}
@ -147,10 +147,10 @@ void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo,AON_ACOMP_CFG_Type *cfg)
void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo)
{
uint32_t tmpVal = 0;
/* Check the parameters */
CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
if(acompNo==AON_ACOMP0_ID){
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP0_CTRL);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_ACOMP0_EN);
@ -173,10 +173,10 @@ void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo)
BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo)
{
uint32_t tmpVal = 0;
/* Check the parameters */
CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP_CTRL);
/* Disable ACOMP first */
if(acompNo==AON_ACOMP0_ID){

164
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_adc.c
View File

@ -106,7 +106,7 @@ static ADC_Gain_Coeff_Type adcGainCoeffCal = {
void ADC_Reset(void)
{
uint32_t regCmd;
/* reset ADC */
regCmd=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,BL_SET_REG_BIT(regCmd,AON_GPADC_SOFT_RST));
@ -125,7 +125,7 @@ void ADC_Reset(void)
void ADC_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_GLOBAL_EN);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
@ -142,7 +142,7 @@ void ADC_Enable(void)
void ADC_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_GLOBAL_EN);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
@ -168,13 +168,13 @@ void ADC_Init(ADC_CFG_Type* cfg)
CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv));
CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1));
CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2));
CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode));
CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode));
CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel));
CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm));
CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref));
CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode));
CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth));
/* config 1 */
regCfg1=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1);
regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_V18_SEL,cfg->v18Sel);
@ -188,7 +188,7 @@ void ADC_Init(ADC_CFG_Type* cfg)
regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_RES_SEL,cfg->resWidth);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG1,regCfg1);
AON_CLK_SET_DUMMY_WAIT;
/* config 2 */
regCfg2=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2);
regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_DLY_SEL,0);
@ -200,7 +200,7 @@ void ADC_Init(ADC_CFG_Type* cfg)
if((cfg->gain1!=ADC_PGA_GAIN_NONE)||(cfg->gain2!=ADC_PGA_GAIN_NONE)){
regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_CHOP_MODE,2);
}else{
regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_CHOP_MODE,1);
regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_CHOP_MODE,1);
}
/* pga_vcmi_en is for mic */
regCfg2=BL_CLR_REG_BIT(regCfg2,AON_GPADC_PGA_VCMI_EN);
@ -216,7 +216,7 @@ void ADC_Init(ADC_CFG_Type* cfg)
regCfg2=BL_SET_REG_BITS_VAL(regCfg2,AON_GPADC_DIFF_MODE,cfg->inputMode);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,regCfg2);
/* calibration offset */
regCalib=BL_RD_REG(AON_BASE,AON_GPADC_REG_DEFINE);
regCalib=BL_SET_REG_BITS_VAL(regCalib,AON_GPADC_OS_CAL_DATA,cfg->offsetCalibVal);
@ -243,16 +243,16 @@ void ADC_Channel_Config(ADC_Chan_Type posCh,ADC_Chan_Type negCh,BL_Fun_Type cont
{
uint32_t regCmd;
uint32_t regCfg1;
CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh));
CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh));
/* set channel */
regCmd=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD);
regCmd=BL_SET_REG_BITS_VAL(regCmd,AON_GPADC_POS_SEL,posCh);
regCmd=BL_SET_REG_BITS_VAL(regCmd,AON_GPADC_NEG_SEL,negCh);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,regCmd);
/* set continuous mode */
regCfg1=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1);
regCfg1=BL_SET_REG_BITS_VAL(regCfg1,AON_GPADC_CONT_CONV_EN,contEn);
@ -276,9 +276,9 @@ void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[],ADC_Chan_Type negChList[]
{
uint32_t tmpVal,i;
uint32_t dealLen;
CHECK_PARAM((scanLength<13));
/* Deal with the first 6 */
dealLen=6;
if(scanLength<dealLen){
@ -291,14 +291,14 @@ void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[],ADC_Chan_Type negChList[]
tmpVal|=(posChList[i]<<(i*5));
}
BL_WR_REG(AON_BASE,AON_GPADC_REG_SCN_POS1,tmpVal);
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_SCN_NEG1);
for(i=0;i<dealLen;i++){
tmpVal=tmpVal&(~(0x1F<<(i*5)));
tmpVal|=(negChList[i]<<(i*5));
}
BL_WR_REG(AON_BASE,AON_GPADC_REG_SCN_NEG1,tmpVal);
/* Set the left channels */
if(scanLength>dealLen){
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_SCN_POS2);
@ -307,7 +307,7 @@ void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[],ADC_Chan_Type negChList[]
tmpVal|=(posChList[i+dealLen]<<(i*5));
}
BL_WR_REG(AON_BASE,AON_GPADC_REG_SCN_POS2,tmpVal);
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_SCN_NEG2);
for(i=0;i<scanLength-dealLen;i++){
tmpVal=tmpVal&(~(0x1F<<(i*5)));
@ -315,9 +315,9 @@ void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[],ADC_Chan_Type negChList[]
}
BL_WR_REG(AON_BASE,AON_GPADC_REG_SCN_NEG2,tmpVal);
}
/* Scan mode */
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1);
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_SCAN_LENGTH,scanLength-1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_CONT_CONV_EN,contEn);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_SCAN_EN);
@ -361,7 +361,7 @@ void ADC_Start(void)
void ADC_Stop(void)
{
uint32_t regCmd;
/* disable convert start */
regCmd=BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD);
regCmd=BL_CLR_REG_BIT(regCmd,AON_GPADC_CONV_START);
@ -387,13 +387,13 @@ void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg)
* DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur
* DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt
*/
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPADC_FIFO_THL,fifoCfg->fifoThreshold);
/* Enable DMA */
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPADC_DMA_EN,fifoCfg->dmaEn);
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
/* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
@ -414,9 +414,9 @@ void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg)
uint8_t ADC_Get_FIFO_Count(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
return BL_GET_REG_BITS_VAL(tmpVal,GPIP_GPADC_FIFO_DATA_COUNT);
}
@ -431,9 +431,9 @@ uint8_t ADC_Get_FIFO_Count(void)
BL_Sts_Type ADC_FIFO_Is_Full(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
if(BL_IS_REG_BIT_SET(tmpVal,GPIP_GPADC_FIFO_FULL)){
return SET;
}else{
@ -452,9 +452,9 @@ BL_Sts_Type ADC_FIFO_Is_Full(void)
BL_Sts_Type ADC_FIFO_Is_Empty(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
if(BL_IS_REG_BIT_SET(tmpVal,GPIP_GPADC_FIFO_NE)){
return RESET;
}else{
@ -574,7 +574,7 @@ void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask)
/* Check the parameters */
CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
switch(intType)
{
case ADC_INT_POS_SATURATION:
@ -600,7 +600,7 @@ void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask)
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
break;
case ADC_INT_FIFO_UNDERRUN:
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
if(intMask == UNMASK){
/* Enable this interrupt */
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_MASK);
@ -611,7 +611,7 @@ void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask)
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
break;
case ADC_INT_FIFO_OVERRUN:
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
if(intMask == UNMASK){
/* Enable this interrupt */
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_MASK);
@ -622,7 +622,7 @@ void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask)
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
break;
case ADC_INT_ADC_READY:
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
if(intMask == UNMASK){
/* Enable this interrupt */
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_MASK);
@ -639,8 +639,8 @@ void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask)
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_MASK);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_MASK);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_MASK);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_MASK);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_MASK);
@ -651,8 +651,8 @@ void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask)
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_MASK);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_MASK);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_MASK);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_MASK);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_RDY_MASK);
@ -678,14 +678,14 @@ void ADC_IntClr(ADC_INT_Type intType)
/* Check the parameters */
CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
switch(intType)
{
case ADC_INT_POS_SATURATION:
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
@ -698,8 +698,8 @@ void ADC_IntClr(ADC_INT_Type intType)
case ADC_INT_NEG_SATURATION:
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
@ -708,12 +708,12 @@ void ADC_IntClr(ADC_INT_Type intType)
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
break;
break;
case ADC_INT_FIFO_UNDERRUN:
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR);
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR);
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
@ -727,8 +727,8 @@ void ADC_IntClr(ADC_INT_Type intType)
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR);
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR);
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
/*Manual reset*/
@ -741,7 +741,7 @@ void ADC_IntClr(ADC_INT_Type intType)
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR);
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR);
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
@ -753,14 +753,14 @@ void ADC_IntClr(ADC_INT_Type intType)
break;
case ADC_INT_ALL:
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_NEG_SATUR_CLR);
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
/*Manual reset*/
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_ISR);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_POS_SATUR_CLR);
@ -768,12 +768,12 @@ void ADC_IntClr(ADC_INT_Type intType)
BL_WR_REG(AON_BASE,AON_GPADC_REG_ISR,tmpVal);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPADC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR);
BL_WR_REG(GPIP_BASE,GPIP_GPADC_CONFIG,tmpVal);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_UNDERRUN_CLR);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_FIFO_OVERRUN_CLR);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPADC_RDY_CLR);
@ -808,7 +808,7 @@ BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType)
/* Check the parameters */
CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
switch(intType)
{
case ADC_INT_POS_SATURATION:
@ -836,7 +836,7 @@ BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType)
default:
break;
}
return bitStatus;
}
@ -853,7 +853,7 @@ void ADC_Int_Callback_Install(ADC_INT_Type intType,intCallback_Type* cbFun)
{
/* Check the parameters */
CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
adcIntCbfArra[intType] = cbFun;
}
@ -880,21 +880,21 @@ void GPADC_DMA_IRQHandler(void)
adcIntCbfArra[ADC_INT_NEG_SATURATION]();
}
}
if( ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN)==SET ){
ADC_IntClr(ADC_INT_FIFO_UNDERRUN);
if(adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL){
adcIntCbfArra[ADC_INT_FIFO_UNDERRUN]();
}
}
if( ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN)==SET ){
ADC_IntClr(ADC_INT_FIFO_OVERRUN);
if(adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL){
adcIntCbfArra[ADC_INT_FIFO_OVERRUN]();
}
}
if( ADC_GetIntStatus(ADC_INT_ADC_READY)==SET ){
ADC_IntClr(ADC_INT_ADC_READY);
if(adcIntCbfArra[ADC_INT_ADC_READY] != NULL){
@ -915,7 +915,7 @@ void GPADC_DMA_IRQHandler(void)
void ADC_Vbat_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_VBAT_EN);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal);
@ -932,7 +932,7 @@ void ADC_Vbat_Enable(void)
void ADC_Vbat_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_VBAT_EN);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal);
@ -949,7 +949,7 @@ void ADC_Vbat_Disable(void)
void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod)
{
uint32_t tmpVal;
CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type));
/* config gpadc_reg_cmd */
@ -986,20 +986,20 @@ void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod)
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_PGA_OS_CAL,0);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal);
/* config 3 */
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG1);
/* set gpadc_dither_en */
tmpVal = BL_SET_REG_BIT(tmpVal,AON_GPADC_DITHER_EN);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG1,tmpVal);
/* set 4000F90C[19](gpadc_mic2_diff) = 1
* debug advise form Ran
/* set 4000F90C[19](gpadc_mic2_diff) = 1
* debug advise form Ran
* 2020.08.26
*/
tmpVal = BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_MIC2_DIFF,1);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
}
@ -1048,7 +1048,7 @@ uint32_t TSEN_Get_V_Error(void)
ADC_Start();
while (ADC_Get_FIFO_Count() == 0)
;
regVal = ADC_Read_FIFO();
regVal = ADC_Read_FIFO();
gainCalEnabled=adcGainCoeffCal.adcGainCoeffEnable;
adcGainCoeffCal.adcGainCoeffEnable=0;
ADC_Parse_Result(&regVal, 1, &result);
@ -1076,25 +1076,25 @@ BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t * tsen_offset)
uint32_t tmpVal=0;
float A1=0.0,A2=0.0,C=0.0,delta=0.0;
Efuse_TSEN_Refcode_Corner_Type trim;
EF_Ctrl_Read_TSEN_Trim(&trim);
if(trim.tsenRefcodeCornerEn){
if(trim.tsenRefcodeCornerParity==EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner,12)){
MSG("TSEN ATE Version = %d\r\n",trim.tsenRefcodeCornerVersion);
*tsen_offset = trim.tsenRefcodeCorner;
if(trim.tsenRefcodeCornerVersion == 0){
/* debug advise by ran
* 2020.9.04
* 2020.9.04
*/
//set 4000F90C[19](gpadc_mic2_diff) = 0
tmpVal = BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_MIC2_DIFF,0);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
for(average_index=0;average_index<50;average_index++){
v_error_sum += TSEN_Get_V_Error();
@ -1110,13 +1110,13 @@ BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t * tsen_offset)
//set 4000F90C[19](gpadc_mic2_diff) = 1
tmpVal = BL_RD_REG(AON_BASE,AON_GPADC_REG_CMD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_MIC2_DIFF,1);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
for(average_index=0;average_index<50;average_index++){
v_error_sum += TSEN_Get_V_Error();
}
v_error_sum /= 50;
v_error_sum /= 50;
MSG("A2 = %d\r\n",v_error_sum);
A2 = v_error_sum;
@ -1134,7 +1134,7 @@ BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t * tsen_offset)
return SUCCESS;
}
}
return ERROR;
}
@ -1198,7 +1198,7 @@ float TSEN_Get_Temp(uint32_t tsen_offset)
while (ADC_Get_FIFO_Count() == 0)
;
regVal = ADC_Read_FIFO();
gainCalEnabled=adcGainCoeffCal.adcGainCoeffEnable;
adcGainCoeffCal.adcGainCoeffEnable=0;
ADC_Parse_Result(&regVal, 1, &result);
@ -1276,7 +1276,7 @@ BL_Err_Type ADC_Mic_Init(ADC_MIC_Type * adc_mic_config)
tmpVal1=BL_SET_REG_BITS_VAL(tmpVal1,AON_GPADC_MICBIAS_EN,adc_mic_config->micBiasEn);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal1);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal1);
return SUCCESS;
@ -1331,9 +1331,9 @@ BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void)
{
Efuse_ADC_Gain_Coeff_Type trim;
uint32_t tmp;
EF_Ctrl_Read_ADC_Gain_Trim(&trim);
if(trim.adcGainCoeffEn){
if(trim.adcGainCoeffParity==EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff,12)){
adcGainCoeffCal.adcGainCoeffEnable = ENABLE;
@ -1347,14 +1347,14 @@ BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void)
adcGainCoeffCal.coe=(1.0+((float)tmp/2048.0));
//printf("coe==%0f\r\n",adcGainCoeffCal.coe);
}else{
adcGainCoeffCal.coe=(1.0-((float)tmp/2048.0));
//printf("coe==%0f\r\n",adcGainCoeffCal.coe);
adcGainCoeffCal.coe=(1.0-((float)tmp/2048.0));
//printf("coe==%0f\r\n",adcGainCoeffCal.coe);
}
return SUCCESS;
}
}
return ERROR;
}

64
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_aon.c
View File

@ -98,14 +98,14 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
{
uint32_t tmpVal = 0;
/* Power up RF for PLL to work */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_MBG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
@ -128,7 +128,7 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_MBG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
return SUCCESS;
}
#endif
@ -182,14 +182,14 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_XTAL_CFG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_XTAL_CAPCODE_IN_AON,capIn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_XTAL_CAPCODE_OUT_AON,capOut);
BL_WR_REG(AON_BASE,AON_XTAL_CFG,tmpVal);
BL602_Delay_US(100);
return SUCCESS;
}
#endif
@ -227,12 +227,12 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_XTAL_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_XTAL_BUF_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
return SUCCESS;
}
#endif
@ -250,14 +250,14 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
{
uint32_t tmpVal = 0;
/* power up RF for PLL to work */
tmpVal=BL_RD_REG(AON_BASE,AON_BG_SYS_TOP);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_BG_SYS_AON);
BL_WR_REG(AON_BASE,AON_BG_SYS_TOP,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
@ -275,14 +275,14 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
{
uint32_t tmpVal = 0;
/* power up RF for PLL to work */
tmpVal=BL_RD_REG(AON_BASE,AON_BG_SYS_TOP);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_BG_SYS_AON);
BL_WR_REG(AON_BASE,AON_BG_SYS_TOP,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
@ -300,13 +300,13 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_LDO11SOC_AON);
BL_WR_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
@ -324,13 +324,13 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO11SOC_AON);
BL_WR_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
@ -348,14 +348,14 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
{
uint32_t tmpVal = 0;
/* ldo15rf power on */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_LDO15RF_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(90);
return SUCCESS;
}
#endif
@ -373,12 +373,12 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
{
uint32_t tmpVal = 0;
/* ldo15rf power off */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO15RF_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
return SUCCESS;
}
#endif
@ -396,14 +396,14 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
{
uint32_t tmpVal = 0;
/* power on sfreg */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_SFREG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(10);
return SUCCESS;
}
#endif
@ -421,12 +421,12 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
{
uint32_t tmpVal = 0;
/* power off sfreg */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_SFREG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
return SUCCESS;
}
#endif
@ -523,9 +523,9 @@ BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
{
uint32_t tmpVal = 0;
CHECK_PARAM((delay<=0x3));
/* config ldo11soc_sstart_delay_aon */
tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_LDO11SOC_SSTART_DELAY_AON,delay);

18
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_common.c
View File

@ -27,7 +27,7 @@
/** @defgroup DRIVER_Private_Variables
* @{
*/
*/
/*@} end of group DRIVER_Private_Variables */
@ -111,7 +111,7 @@ void Trap_Handler(void){
}
/****************************************************************************//**
* @brief delay us
* @brief delay us
*
* @param[in] core: systemcoreclock
*
@ -182,9 +182,9 @@ void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt)
{
uint32_t codeAddress = 0;
uint32_t divVal = 40;
codeAddress = (uint32_t)&ASM_Delay_Us;
/* 1M=100K*10, so multiple is 10 */
/* loop function take 4 instructions, so instructionNum is 4 */
/* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */
@ -196,7 +196,7 @@ void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt)
divVal = 80;
}
}
__asm__ __volatile__(
".align 4\n\t"
"lw a4,%1\n\t"
@ -235,7 +235,7 @@ void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt)
/****************************************************************************//**
* @brief delay us
* @brief delay us
*
* @param[in] cnt: delay cnt us
*
@ -249,7 +249,7 @@ void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt)
}
/****************************************************************************//**
* @brief delay ms
* @brief delay ms
*
* @param[in] cnt: delay cnt ms
*
@ -261,7 +261,7 @@ void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt)
{
uint32_t i = 0;
uint32_t count = 0;
if(cnt>=1024){
/* delay (n*1024) ms */
count = 1024;
@ -337,7 +337,7 @@ void* ATTR_TCM_SECTION BL602_MemCpy_Fast(void *pdst, const void *psrc, uint32_t
uint32_t left,done,i=0;
uint8_t *dst=(uint8_t *)pdst;
uint8_t *src=(uint8_t *)psrc;
if(((uint32_t)dst&0x3)==0&&((uint32_t)src&0x3)==0){
BL602_MemCpy4((uint32_t *)dst,(const uint32_t *)src,n>>2);
left=n%4;

2
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_common_ext.c
View File

@ -27,7 +27,7 @@
/** @defgroup DRIVER_Private_Variables
* @{
*/
*/
/*@} end of group DRIVER_Private_Variables */

88
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_dac.c
View File

@ -96,15 +96,15 @@
void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));
/* Set DAC config */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_REF_SEL,cfg->refSel);
if(ENABLE==cfg->resetChanA){
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
__NOP();
__NOP();
@ -112,17 +112,17 @@ void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg)
__NOP();
}
if(ENABLE==cfg->resetChanB){
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
}
/* Clear reset */
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
}
@ -137,16 +137,16 @@ void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg)
void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));
/* Set channel A config */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_ACTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_OUTMUX,cfg->outMux);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOA_EN,cfg->outputEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_EN,cfg->chanEn);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_ACTRL,tmpVal);
}
@ -161,16 +161,16 @@ void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg)
void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));
/* Set channel A config */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_BCTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_OUTMUX,cfg->outMux);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOB_EN,cfg->outputEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_EN,cfg->chanEn);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_BCTRL,tmpVal);
}
@ -185,9 +185,9 @@ void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg)
void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src));
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_B_SEL,src);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
@ -204,9 +204,9 @@ void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src)
void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src));
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_A_SEL,src);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
@ -223,9 +223,9 @@ void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src)
void GPIP_Set_DAC_Mod_SEL(GPIP_DAC_MOD_Type mod)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(mod));
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_MODE,mod);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
@ -242,7 +242,7 @@ void GPIP_Set_DAC_Mod_SEL(GPIP_DAC_MOD_Type mod)
void GPIP_DAC_ChanB_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_EN2);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
@ -259,7 +259,7 @@ void GPIP_DAC_ChanB_Enable(void)
void GPIP_DAC_ChanB_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_EN2);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
@ -276,7 +276,7 @@ void GPIP_DAC_ChanB_Disable(void)
void GPIP_DAC_ChanA_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_EN);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
@ -293,7 +293,7 @@ void GPIP_DAC_ChanA_Enable(void)
void GPIP_DAC_ChanA_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_EN);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
@ -310,9 +310,9 @@ void GPIP_DAC_ChanA_Disable(void)
void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt));
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_DMA_FORMAT,fmt);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal);
@ -329,7 +329,7 @@ void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt)
void GPIP_Set_DAC_DMA_TX_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_DMA_TX_EN);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal);
@ -346,7 +346,7 @@ void GPIP_Set_DAC_DMA_TX_Enable(void)
void GPIP_Set_DAC_DMA_TX_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_DMA_TX_EN);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal);
@ -376,16 +376,16 @@ void GPIP_DAC_DMA_WriteData(uint32_t data)
BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type* cfg)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));
CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->mod));
CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt));
/* AON Set DAC config */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_REF_SEL,cfg->refSel);
if(ENABLE==cfg->resetChanA){
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
__NOP();
__NOP();
@ -393,17 +393,17 @@ BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type* cfg)
__NOP();
}
if(ENABLE==cfg->resetChanB){
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
}
/* AON Clear reset */
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
if(cfg->dmaEn == DISABLE && cfg->mod == GPIP_DAC_MOD_512K){
@ -414,7 +414,7 @@ BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type* cfg)
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_MODE,cfg->mod);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* GPIP Set DMA config */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_DMA_TX_EN,cfg->dmaEn);
@ -435,19 +435,19 @@ BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type* cfg)
void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src));
/* GPIP select source */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_A_SEL,cfg->src);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* GPIP enable or disable channel */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_EN,cfg->chanEn);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* AON enable or disable channel */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_ACTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOA_EN,cfg->outputEn);
@ -466,19 +466,19 @@ void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg)
void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src));
/* GPIP select source */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_B_SEL,cfg->src);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* GPIP enable or disable channel */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_EN2,cfg->chanEn);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* AON enable or disable channel */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_BCTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOB_EN,cfg->outputEn);
@ -497,9 +497,9 @@ void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg)
void GLB_DAC_Set_ChanA_Value(uint16_t val)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_DATA);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_DATA,val);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_DATA,val);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_DATA,tmpVal);
}
@ -514,7 +514,7 @@ void GLB_DAC_Set_ChanA_Value(uint16_t val)
void GLB_DAC_Set_ChanB_Value(uint16_t val)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_DATA);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_DATA,val);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_DATA,tmpVal);

6
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_dma.c
View File

@ -454,7 +454,7 @@ BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct)
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;
if(dmaPpStruct->is_single_mode == 1){
/*
/*
* if is is_single_mode is 1 ping-pong will only run once atfer start singal
* or ping-pong will run forever unless stop singal occour
*/
@ -522,11 +522,11 @@ BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct,uin
dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl ;
dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len;
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp;
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp;
dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl ;
dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len;
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp;
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp;
DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg);
DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]);

346
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_glb.c
View File

File diff suppressed because it is too large Load Diff

2
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_hbn.c
View File

@ -114,7 +114,7 @@ void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
/* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */
HBN_Hw_Pu_Pd_Cfg(DISABLE);
HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));
if(cfg->gpioWakeupSrc!=0){
HBN_Aon_Pad_IeSmt_Cfg(ENABLE);

202
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_ir.c
View File

@ -111,7 +111,7 @@ static intCallback_Type * irIntCbfArra[IR_INT_ALL]= {NULL,NULL};
void __IRQ IRRX_IRQHandler(void)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS);
if(BL_IS_REG_BIT_SET(tmpVal,IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal,IR_CR_IRRX_END_MASK)){
BL_WR_REG(IR_BASE,IRRX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_CLR));
@ -134,7 +134,7 @@ void __IRQ IRRX_IRQHandler(void)
void __IRQ IRTX_IRQHandler(void)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(IR_BASE,IRTX_INT_STS);
if(BL_IS_REG_BIT_SET(tmpVal,IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal,IR_CR_IRTX_END_MASK)){
BL_WR_REG(IR_BASE,IRTX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_END_CLR));
@ -156,7 +156,7 @@ void __IRQ IRTX_IRQHandler(void)
BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG);
/* Set data bit */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_DATA_NUM,irTxCfg->dataBits-1);
@ -175,10 +175,10 @@ BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg)
ENABLE == irTxCfg->outputModulation ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_MOD_EN)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_MOD_EN));
/* Enable or disable output inverse */
ENABLE == irTxCfg->outputInverse ? (tmpVal=BL_SET_REG_BIT(tmpVal,IR_CR_IRTX_OUT_INV)):(tmpVal=BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_OUT_INV));
/* Write back */
BL_WR_REG(IR_BASE,IRTX_CONFIG,tmpVal);
return SUCCESS;
}
@ -193,7 +193,7 @@ BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg)
BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(IR_BASE,IRTX_PW);
/* Set logic 0 pulse phase 0 width */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_LOGIC0_PH0_W,irTxPulseWidthCfg->logic0PulseWidth_0-1);
@ -212,7 +212,7 @@ BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg)
/* Set tail pulse phase 1 width */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_TAIL_PH1_W,irTxPulseWidthCfg->tailPulseWidth_1-1);
BL_WR_REG(IR_BASE,IRTX_PW,tmpVal);
tmpVal = BL_RD_REG(IR_BASE,IRTX_PULSE_WIDTH);
/* Set modulation phase 0 width */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_MOD_PH0_W,irTxPulseWidthCfg->moduWidth_0-1);
@ -221,7 +221,7 @@ BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg)
/* Set pulse width unit */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_PW_UNIT,irTxPulseWidthCfg->pulseWidthUnit-1);
BL_WR_REG(IR_BASE,IRTX_PULSE_WIDTH,tmpVal);
return SUCCESS;
}
@ -244,7 +244,7 @@ BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWid
BL_WR_REG(IR_BASE,IRTX_SWM_PW_5,irTxSWMPulseWidthCfg->swmData5);
BL_WR_REG(IR_BASE,IRTX_SWM_PW_6,irTxSWMPulseWidthCfg->swmData6);
BL_WR_REG(IR_BASE,IRTX_SWM_PW_7,irTxSWMPulseWidthCfg->swmData7);
return SUCCESS;
}
@ -259,10 +259,10 @@ BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWid
BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode));
tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG);
/* Set rx mode */
switch(irRxCfg->rxMode)
@ -287,7 +287,7 @@ BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg)
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_DEG_CNT,irRxCfg->DeglitchCnt);
/* Write back */
BL_WR_REG(IR_BASE,IRRX_CONFIG,tmpVal);
tmpVal = BL_RD_REG(IR_BASE,IRRX_PW_CONFIG);
/* Set pulse width threshold to trigger end condition */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_END_TH,irRxCfg->endThreshold-1);
@ -295,7 +295,7 @@ BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg)
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_DATA_TH,irRxCfg->dataThreshold-1);
/* Write back */
BL_WR_REG(IR_BASE,IRRX_PW_CONFIG,tmpVal);
return SUCCESS;
}
@ -310,7 +310,7 @@ BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg)
BL_Err_Type IR_DeInit(void)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_IRR);
return SUCCESS;
}
@ -325,10 +325,10 @@ BL_Err_Type IR_DeInit(void)
BL_Err_Type IR_Enable(IR_Direction_Type direct)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct));
if(direct == IR_TX || direct == IR_TXRX){
/* Enable ir tx unit */
tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG);
@ -340,7 +340,7 @@ BL_Err_Type IR_Enable(IR_Direction_Type direct)
tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG);
BL_WR_REG(IR_BASE,IRRX_CONFIG,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_EN));
}
return SUCCESS;
}
@ -355,10 +355,10 @@ BL_Err_Type IR_Enable(IR_Direction_Type direct)
BL_Err_Type IR_Disable(IR_Direction_Type direct)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct));
if(direct == IR_TX || direct == IR_TXRX){
/* Disable ir tx unit */
tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG);
@ -370,7 +370,7 @@ BL_Err_Type IR_Disable(IR_Direction_Type direct)
tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG);
BL_WR_REG(IR_BASE,IRRX_CONFIG,BL_CLR_REG_BIT(tmpVal,IR_CR_IRRX_EN));
}
return SUCCESS;
}
@ -385,7 +385,7 @@ BL_Err_Type IR_Disable(IR_Direction_Type direct)
BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM)
{
uint32_t tmpVal;
/* Enable or disable tx swm */
tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG);
if(ENABLE == txSWM){
@ -393,7 +393,7 @@ BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM)
}else{
BL_WR_REG(IR_BASE,IRTX_CONFIG,BL_CLR_REG_BIT(tmpVal,IR_CR_IRTX_SWM_EN));
}
return SUCCESS;
}
@ -408,11 +408,11 @@ BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM)
BL_Err_Type IR_RxFIFOClear(void)
{
uint32_t tmpVal;
/* Clear rx fifo */
tmpVal = BL_RD_REG(IR_BASE,IRRX_SWM_FIFO_CONFIG_0);
BL_WR_REG(IR_BASE,IRRX_SWM_FIFO_CONFIG_0,BL_SET_REG_BIT(tmpVal,IR_RX_FIFO_CLR));
return SUCCESS;
}
@ -429,7 +429,7 @@ BL_Err_Type IR_SendData(IR_Word_Type irWord,uint32_t data)
{
/* Check the parameters */
CHECK_PARAM(IS_IR_WORD_TYPE(irWord));
/* Write word 0 or word 1 */
if(IR_WORD_0 == irWord){
BL_WR_REG(IR_BASE,IRTX_DATA_WORD0,data);
@ -437,7 +437,7 @@ BL_Err_Type IR_SendData(IR_Word_Type irWord,uint32_t data)
else{
BL_WR_REG(IR_BASE,IRTX_DATA_WORD1,data);
}
return SUCCESS;
}
@ -457,18 +457,18 @@ BL_Err_Type IR_SWMSendData(uint16_t *data,uint8_t length)
uint32_t tmpVal;
uint32_t pwVal = 0;
uint32_t count = (length+7)/8;
/* Search for min value */
for(i=1;i<length;i++){
if(minData>data[i] && data[i]!=0){
minData = data[i];
}
}
/* Set pulse width unit */
tmpVal = BL_RD_REG(IR_BASE,IRTX_PULSE_WIDTH);
BL_WR_REG(IR_BASE,IRTX_PULSE_WIDTH,BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_PW_UNIT,minData));
/* Set tx SWM pulse width data as multiples of pulse width unit */
for(i=0;i<count;i++){
pwVal = 0;
@ -486,7 +486,7 @@ BL_Err_Type IR_SWMSendData(uint16_t *data,uint8_t length)
*(volatile uint32_t*)(IR_BASE+IRTX_SWM_PW_0_OFFSET+i*4) = pwVal;
}
}
return SUCCESS;
}
@ -502,36 +502,36 @@ BL_Err_Type IR_SWMSendData(uint16_t *data,uint8_t length)
BL_Err_Type IR_SendCommand(uint32_t word1,uint32_t word0)
{
uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;
/* Write data */
IR_SendData(IR_WORD_1,word1);
IR_SendData(IR_WORD_0,word0);
/* Mask tx interrupt */
IR_IntMask(IR_INT_TX,MASK);
/* Clear tx interrupt */
IR_ClrIntStatus(IR_INT_TX);
/* Enable ir tx */
IR_Enable(IR_TX);
/* Wait for tx interrupt */
while(SET != IR_GetIntStatus(IR_INT_TX)){
timeoutCnt--;
if(timeoutCnt == 0){
IR_Disable(IR_TX);
return TIMEOUT;
}
}
/* Disable ir tx */
IR_Disable(IR_TX);
/* Clear tx interrupt */
IR_ClrIntStatus(IR_INT_TX);
return SUCCESS;
}
@ -547,35 +547,35 @@ BL_Err_Type IR_SendCommand(uint32_t word1,uint32_t word0)
BL_Err_Type IR_SWMSendCommand(uint16_t* data,uint8_t length)
{
uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;
/* Write fifo */
IR_SWMSendData(data,length);
/* Mask tx interrupt */
IR_IntMask(IR_INT_TX,MASK);
/* Clear tx interrupt */
IR_ClrIntStatus(IR_INT_TX);
/* Enable ir tx */
IR_Enable(IR_TX);
/* Wait for tx interrupt */
while(SET != IR_GetIntStatus(IR_INT_TX)){
timeoutCnt--;
if(timeoutCnt == 0){
IR_Disable(IR_TX);
return TIMEOUT;
}
}
/* Disable ir tx */
IR_Disable(IR_TX);
/* Clear tx interrupt */
IR_ClrIntStatus(IR_INT_TX);
return SUCCESS;
}
@ -591,9 +591,9 @@ BL_Err_Type IR_SWMSendCommand(uint16_t* data,uint8_t length)
BL_Err_Type IR_SendNEC(uint8_t address,uint8_t command)
{
uint32_t tmpVal = ((~command&0xff)<<24)+(command<<16)+((~address&0xff)<<8)+address;
IR_SendCommand(0,tmpVal);
return SUCCESS;
}
@ -609,10 +609,10 @@ BL_Err_Type IR_SendNEC(uint8_t address,uint8_t command)
BL_Err_Type IR_IntMask(IR_INT_Type intType,BL_Mask_Type intMask)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_IR_INT_TYPE(intType));
if(intType == IR_INT_TX || intType == IR_INT_ALL){
/* Mask or unmask tx interrupt */
tmpVal = BL_RD_REG(IR_BASE,IRTX_INT_STS);
@ -624,7 +624,7 @@ BL_Err_Type IR_IntMask(IR_INT_Type intType,BL_Mask_Type intMask)
tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS);
BL_WR_REG(IR_BASE,IRRX_INT_STS,BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_END_MASK,intMask));
}
return SUCCESS;
}
@ -639,10 +639,10 @@ BL_Err_Type IR_IntMask(IR_INT_Type intType,BL_Mask_Type intMask)
BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_IR_INT_TYPE(intType));
if(intType == IR_INT_TX || intType == IR_INT_ALL){
/* Clear tx interrupt */
tmpVal = BL_RD_REG(IR_BASE,IRTX_INT_STS);
@ -654,7 +654,7 @@ BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType)
tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS);
BL_WR_REG(IR_BASE,IRRX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_CLR));
}
return SUCCESS;
}
@ -671,9 +671,9 @@ BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType,intCallback_Type *cbFun)
{
/* Check the parameters */
CHECK_PARAM(IS_IR_INT_TYPE(intType));
irIntCbfArra[intType] = cbFun;
return SUCCESS;
}
@ -688,10 +688,10 @@ BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType,intCallback_Type *cbFun)
BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType)
{
uint32_t tmpVal = 0;
/* Check the parameters */
CHECK_PARAM(IS_IR_INT_TYPE(intType));
/* Read tx or rx interrupt status */
if(IR_INT_TX == intType){
tmpVal = BL_RD_REG(IR_BASE,IRTX_INT_STS);
@ -701,7 +701,7 @@ BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType)
tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal,IRRX_END_INT);
}
if(tmpVal)
{
return SET;
@ -721,10 +721,10 @@ BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType)
BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_IR_FIFOSTATUS_TYPE(fifoSts));
/* Read rx fifo status */
tmpVal = BL_RD_REG(IR_BASE,IRRX_SWM_FIFO_CONFIG_0);
if(fifoSts == IR_RX_FIFO_UNDERFLOW){
@ -732,7 +732,7 @@ BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts)
}else{
tmpVal = BL_GET_REG_BITS_VAL(tmpVal,IR_RX_FIFO_OVERFLOW);
}
if(tmpVal){
return SET;
}else{
@ -751,10 +751,10 @@ BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts)
uint32_t IR_ReceiveData(IR_Word_Type irWord)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_IR_WORD_TYPE(irWord));
/* Read word 0 or word 1 */
if(IR_WORD_0 == irWord){
tmpVal = BL_RD_REG(IR_BASE,IRRX_DATA_WORD0);
@ -777,7 +777,7 @@ uint32_t IR_ReceiveData(IR_Word_Type irWord)
uint8_t IR_SWMReceiveData(uint16_t* data,uint8_t length)
{
uint8_t rxLen = 0;
while(rxLen<length && IR_GetRxFIFOCount()>0){
/* Read data */
data[rxLen++] = BL_RD_REG(IR_BASE,IRRX_SWM_FIFO_RDATA)&0xffff;
@ -797,14 +797,14 @@ uint8_t IR_SWMReceiveData(uint16_t* data,uint8_t length)
BL_Err_Type IR_ReceiveNEC(uint8_t* address,uint8_t* command)
{
uint32_t tmpVal = IR_ReceiveData(IR_WORD_0);
*address = tmpVal&0xff;
*command = (tmpVal>>16)&0xff;
if((~(*address)&0xff) != ((tmpVal>>8)&0xff) || (~(*command)&0xff) != ((tmpVal>>24)&0xff)){
return ERROR;
}
return SUCCESS;
}
@ -819,11 +819,11 @@ BL_Err_Type IR_ReceiveNEC(uint8_t* address,uint8_t* command)
uint8_t IR_GetRxDataBitCount(void)
{
uint32_t tmpVal;
/* Read rx data bit count */
tmpVal = BL_RD_REG(IR_BASE,IRRX_DATA_COUNT);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal,IR_STS_IRRX_DATA_CNT);
return tmpVal;
}
@ -838,11 +838,11 @@ uint8_t IR_GetRxDataBitCount(void)
uint8_t IR_GetRxFIFOCount(void)
{
uint32_t tmpVal;
/* Read rx fifo count */
tmpVal = BL_RD_REG(IR_BASE,IRRX_SWM_FIFO_CONFIG_0);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal,IR_RX_FIFO_CNT);
return tmpVal;
}
@ -859,7 +859,7 @@ IR_RxMode_Type IR_LearnToInit(uint32_t* data,uint8_t* length)
{
uint32_t tmpVal;
uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT;
/* Disable rx,set rx in software mode and enable rx input inverse */
tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG);
tmpVal = BL_CLR_REG_BIT(tmpVal,IR_CR_IRRX_EN);
@ -869,38 +869,38 @@ IR_RxMode_Type IR_LearnToInit(uint32_t* data,uint8_t* length)
/* Set pulse width threshold to trigger end condition */
tmpVal = BL_RD_REG(IR_BASE,IRRX_PW_CONFIG);
BL_WR_REG(IR_BASE,IRRX_PW_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRRX_END_TH,19999));
/* Clear and mask rx interrupt */
tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS);
tmpVal = BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_MASK);
BL_WR_REG(IR_BASE,IRRX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_CLR));
/* Enable rx */
tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG);
BL_WR_REG(IR_BASE,IRRX_CONFIG,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_EN));
/* Wait for rx interrupt */
while(SET != IR_GetIntStatus(IR_INT_RX)){
timeoutCnt--;
if(timeoutCnt == 0){
IR_Disable(IR_RX);
return TIMEOUT;
}
}
/* Disable rx */
tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG);
BL_WR_REG(IR_BASE,IRRX_CONFIG,BL_CLR_REG_BIT(tmpVal,IR_CR_IRRX_EN));
/* Clear rx interrupt */
tmpVal = BL_RD_REG(IR_BASE,IRRX_INT_STS);
BL_WR_REG(IR_BASE,IRRX_INT_STS,BL_SET_REG_BIT(tmpVal,IR_CR_IRRX_END_CLR));
/*Receive data */
*length = IR_GetRxFIFOCount();
*length = IR_SWMReceiveData((uint16_t*)data,*length);
/* Judge protocol type */
if(NEC_HEAD_H_MIN<(data[0]&0xffff)&&(data[0]&0xffff)<NEC_HEAD_H_MAX&&NEC_HEAD_L_MIN<(data[0]>>16)&&(data[0]>>16)<NEC_HEAD_L_MAX&&NEC_BIT0_H_MIN<(data[1]&0xffff)&&(data[1]&0xffff)<NEC_BIT0_H_MAX){
/* Set rx in NEC mode */
@ -915,7 +915,7 @@ IR_RxMode_Type IR_LearnToInit(uint32_t* data,uint8_t* length)
BL_WR_REG(IR_BASE,IRTX_PW,0x7f2000);
/* Set modulation phase width and pulse width unit */
BL_WR_REG(IR_BASE,IRTX_PULSE_WIDTH,0x22110464);
return IR_RX_NEC;
}
else if(RC5_ONE_PLUSE_MIN<(data[0]&0xffff)&&(data[0]&0xffff)<RC5_ONE_PLUSE_MAX&&((RC5_ONE_PLUSE_MIN<(data[0]>>16)&&(data[0]>>16)<RC5_ONE_PLUSE_MAX)||(RC5_TWO_PLUSE_MIN<(data[0]>>16)&&(data[0]>>16)<RC5_TWO_PLUSE_MAX))&& \
@ -932,7 +932,7 @@ IR_RxMode_Type IR_LearnToInit(uint32_t* data,uint8_t* length)
BL_WR_REG(IR_BASE,IRTX_PW,0);
/* Set modulation phase width and pulse width unit */
BL_WR_REG(IR_BASE,IRTX_PULSE_WIDTH,0x221106f1);
return IR_RX_RC5;
}else if((data[0]>>16) != 0){
/* Set tx in software mode */
@ -940,7 +940,7 @@ IR_RxMode_Type IR_LearnToInit(uint32_t* data,uint8_t* length)
BL_WR_REG(IR_BASE,IRTX_CONFIG,*length<<12 | 0xc);
/* Set modulation phase width */
BL_WR_REG(IR_BASE,IRTX_PULSE_WIDTH,0x22110000);
return IR_RX_SWM;
}else{
tmpVal = BL_RD_REG(IR_BASE,IRRX_CONFIG);
@ -968,36 +968,36 @@ uint8_t IR_LearnToReceive(IR_RxMode_Type mode,uint32_t* data)
{
uint8_t length = 0;
uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_IR_RXMODE_TYPE(mode));
/* Disable ir rx */
IR_Disable(IR_RX);
/* Clear and mask rx interrupt */
IR_ClrIntStatus(IR_INT_RX);
IR_IntMask(IR_INT_RX,MASK);
/* Enable ir rx */
IR_Enable(IR_RX);
/* Wait for rx interrupt */
while(SET != IR_GetIntStatus(IR_INT_RX)){
timeoutCnt--;
if(timeoutCnt == 0){
IR_Disable(IR_RX);
return TIMEOUT;
}
}
/* Disable ir rx */
IR_Disable(IR_RX);
/* Clear rx interrupt */
IR_ClrIntStatus(IR_INT_RX);
/* Receive data according to mode */
if(mode == IR_RX_NEC || mode == IR_RX_RC5){
/* Get data bit count */
@ -1008,7 +1008,7 @@ uint8_t IR_LearnToReceive(IR_RxMode_Type mode,uint32_t* data)
length = IR_GetRxFIFOCount();
length = IR_SWMReceiveData((uint16_t*)data,length);
}
return length;
}
@ -1026,23 +1026,23 @@ uint8_t IR_LearnToReceive(IR_RxMode_Type mode,uint32_t* data)
BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode,uint32_t* data,uint8_t length)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_IR_RXMODE_TYPE(mode));
/* Set send length */
tmpVal = BL_RD_REG(IR_BASE,IRTX_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,IR_CR_IRTX_DATA_NUM,length-1);
BL_WR_REG(IR_BASE,IRTX_CONFIG,tmpVal);
if(mode == IR_RX_NEC || mode == IR_RX_RC5){
IR_SendCommand(0,data[0]);
}else{
IR_SWMSendCommand((uint16_t*)data,length);
}
return SUCCESS;
}
}
/*@} end of group IR_Public_Functions */

54
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_l1c.c
View File

@ -102,14 +102,14 @@ BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap)
{
uint32_t tmpVal = 0;
uint8_t cacheEn = 0;
tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG);
cacheEn = BL_IS_REG_BIT_SET(L1C_BASE,L1C_CACHEABLE);
if(cacheEn != 0){
tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_CACHEABLE);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
}
tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG);
if(wrap == ENABLE){
tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_WRAP_DIS);
@ -117,7 +117,7 @@ BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap)
tmpVal=BL_SET_REG_BIT(tmpVal,L1C_WRAP_DIS);
}
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
if(cacheEn != 0){
tmpVal=BL_SET_REG_BIT(tmpVal,L1C_CACHEABLE);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
@ -141,18 +141,18 @@ BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal)
{
uint32_t tmpVal = 0;
uint8_t cacheEn = 0;
tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG);
cacheEn = BL_IS_REG_BIT_SET(L1C_BASE,L1C_CACHEABLE);
if(cacheEn != 0){
tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_CACHEABLE);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
}
tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,L1C_WAY_DIS,disableVal);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
if(cacheEn != 0){
tmpVal=BL_SET_REG_BIT(tmpVal,L1C_CACHEABLE);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
@ -175,7 +175,7 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG);
if(enable){
tmpVal=BL_SET_REG_BIT(tmpVal,L1C_IROM_2T_ACCESS);
@ -183,7 +183,7 @@ BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_IROM_2T_ACCESS);
}
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
return SUCCESS;
}
#endif
@ -199,15 +199,15 @@ BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg)
{
uint32_t tmpVal = 0;
CHECK_PARAM((l1cBmxCfg->timeoutEn)<=0xF);
tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,L1C_BMX_TIMEOUT_EN,l1cBmxCfg->timeoutEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,L1C_BMX_ERR_EN,l1cBmxCfg->errEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,L1C_BMX_ARB_MODE,l1cBmxCfg->arbMod);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
return SUCCESS;
}
@ -222,11 +222,11 @@ BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg)
BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN);
tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_BMX_ERR_ADDR_DIS);
BL_WR_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN,tmpVal);
return SUCCESS;
}
@ -241,11 +241,11 @@ BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void)
BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN);
tmpVal=BL_SET_REG_BIT(tmpVal,L1C_BMX_ERR_ADDR_DIS);
BL_WR_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN,tmpVal);
return SUCCESS;
}
@ -260,11 +260,11 @@ BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void)
BL_Err_Type L1C_BMX_BusErrResponse_Enable(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG);
tmpVal=BL_SET_REG_BIT(tmpVal,L1C_BMX_ERR_EN);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
return SUCCESS;
}
@ -279,11 +279,11 @@ BL_Err_Type L1C_BMX_BusErrResponse_Enable(void)
BL_Err_Type L1C_BMX_BusErrResponse_Disable(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(L1C_BASE,L1C_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_BMX_ERR_EN);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
return SUCCESS;
}
@ -298,9 +298,9 @@ BL_Err_Type L1C_BMX_BusErrResponse_Disable(void)
BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType)
{
uint32_t tmpVal = 0;
CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType));
tmpVal=BL_RD_REG(L1C_BASE,L1C_BMX_ERR_ADDR_EN);
if(errType==L1C_BMX_BUS_ERR_TRUSTZONE_DECODE){
return BL_GET_REG_BITS_VAL(tmpVal,L1C_BMX_ERR_TZ)?SET:RESET;
@ -336,7 +336,7 @@ BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType,intCal
CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType));
l1cBmxErrIntCbfArra[intType] = cbFun;
return SUCCESS;
}
@ -352,13 +352,13 @@ BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType,intCal
void __IRQ L1C_BMX_ERR_IRQHandler(void)
{
L1C_BMX_ERR_INT_Type intType;
for(intType=L1C_BMX_ERR_INT_ERR;intType<L1C_BMX_ERR_INT_ALL;intType++){
if(l1cBmxErrIntCbfArra[intType]!=NULL){
l1cBmxErrIntCbfArra[intType]();
}
}
while(1){
MSG("L1C_BMX_ERR_IRQHandler\r\n");
BL602_Delay_MS(1000);
@ -380,7 +380,7 @@ BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,int
CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType));
l1cBmxToIntCbfArra[intType] = cbFun;
return SUCCESS;
}
@ -396,13 +396,13 @@ BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,int
void __IRQ L1C_BMX_TO_IRQHandler(void)
{
L1C_BMX_TO_INT_Type intType;
for(intType=L1C_BMX_TO_INT_TIMEOUT;intType<L1C_BMX_TO_INT_ALL;intType++){
if(l1cBmxToIntCbfArra[intType]!=NULL){
l1cBmxToIntCbfArra[intType]();
}
}
while(1){
MSG("L1C_BMX_TO_IRQHandler\r\n");
BL602_Delay_MS(1000);

120
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_pds.c
View File

@ -100,15 +100,15 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void)
{
uint32_t tmpVal = 0;
tmpVal = *(uint32_t *)0x40000014;
tmpVal = tmpVal | (1<<14);
*(uint32_t *)0x40000014 = tmpVal;
tmpVal = *(uint32_t *)0x40000014;
tmpVal = tmpVal & ~(1<<14);
*(uint32_t *)0x40000014 = tmpVal;
return SUCCESS;
}
#endif
@ -127,7 +127,7 @@ BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void)
__WEAK
BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,uint32_t pdsSleepCnt)
{
/* PDS sleep time 0 <=> sleep forever */
/* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
/* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
@ -138,10 +138,10 @@ BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,ui
}else{
BL_WR_REG(PDS_BASE,PDS_TIME1,pdsSleepCnt-PDS_WARMUP_LATENCY_CNT);
}
/* PDS_CTL4 config */
BL_WR_REG(PDS_BASE,PDS_CTL4,*(uint32_t *)cfg4);
/* PDS_CTL config */
if(cfg->pdsStart){
BL_WR_REG(PDS_BASE,PDS_CTL,(*(uint32_t *)cfg&~(1<<0)));
@ -149,7 +149,7 @@ BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,ui
}else{
BL_WR_REG(PDS_BASE,PDS_CTL,*(uint32_t *)cfg);
}
return SUCCESS;
}
#endif
@ -169,10 +169,10 @@ BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2,PDS_CTL3_Type
{
/* PDS_CTL2 config */
BL_WR_REG(PDS_BASE,PDS_CTL2,*(uint32_t *)cfg2);
/* PDS_CTL3 config */
BL_WR_REG(PDS_BASE,PDS_CTL3,*(uint32_t *)cfg3);
return SUCCESS;
}
#endif
@ -190,7 +190,7 @@ __WEAK
BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg)
{
uint32_t tmpVal = 0;
if(NULL==ramCfg){
return SUCCESS;
}
@ -201,17 +201,17 @@ BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg)
/* enter bist mode (make ram ret) */
tmpVal = tmpVal|(0x1<<3);
BL_WR_REG(GLB_BASE,GLB_MBIST_CTL,tmpVal);
/* PDS_RAM1 config */
BL_WR_REG(PDS_BASE,PDS_RAM1,*(uint32_t *)ramCfg);
tmpVal = BL_RD_REG(GLB_BASE,GLB_MBIST_CTL);
/* exit bist mode (make ram idle/slp) */
//tmpVal = tmpVal&~0x1F;
/* exit bist mode (make ram ret) */
tmpVal = tmpVal&~(0x1<<3);
BL_WR_REG(GLB_BASE,GLB_MBIST_CTL,tmpVal);
return SUCCESS;
}
#endif
@ -234,7 +234,7 @@ BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *d
PDS_RAM_Config(ramCfg);
PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2),(PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3));
PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl),(PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4),pdsSleepCnt);
return SUCCESS;
}
#endif
@ -251,7 +251,7 @@ BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *d
BL_Err_Type PDS_IntMask(PDS_INT_Type intType,BL_Mask_Type intMask)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(PDS_BASE,PDS_INT);
if(intMask!=UNMASK){
tmpVal = tmpVal|(1<<(intType+PDS_INT_MASK_BIT_OFFSET));
@ -259,7 +259,7 @@ BL_Err_Type PDS_IntMask(PDS_INT_Type intType,BL_Mask_Type intMask)
tmpVal = tmpVal&~(1<<(intType+PDS_INT_MASK_BIT_OFFSET));
}
BL_WR_REG(PDS_BASE,PDS_INT,tmpVal);
return SUCCESS;
}
@ -287,19 +287,19 @@ BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)
BL_Err_Type PDS_IntClear(void)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(PDS_BASE,PDS_INT);
tmpVal = BL_CLR_REG_BIT(tmpVal,PDS_CR_PDS_INT_CLR);
BL_WR_REG(PDS_BASE,PDS_INT,tmpVal);
tmpVal = BL_RD_REG(PDS_BASE,PDS_INT);
tmpVal = BL_SET_REG_BIT(tmpVal,PDS_CR_PDS_INT_CLR);
BL_WR_REG(PDS_BASE,PDS_INT,tmpVal);
tmpVal = BL_RD_REG(PDS_BASE,PDS_INT);
tmpVal = BL_CLR_REG_BIT(tmpVal,PDS_CR_PDS_INT_CLR);
BL_WR_REG(PDS_BASE,PDS_INT,tmpVal);
return SUCCESS;
}
@ -354,7 +354,7 @@ PDS_STS_Type PDS_Get_PdsStstus(void)
BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType,intCallback_Type* cbFun)
{
pdsIntCbfArra[intType][0] = cbFun;
return SUCCESS;
}
@ -372,7 +372,7 @@ BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
{
Efuse_Ana_RC32M_Trim_Type trim;
int32_t tmpVal = 0;
EF_Ctrl_Read_RC32M_Trim(&trim);
if(trim.trimRc32mExtCodeEn){
if(trim.trimRc32mCodeFrExtParity==EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt,8)){
@ -384,7 +384,7 @@ BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
return SUCCESS;
}
}
return ERROR;
}
#endif
@ -402,12 +402,12 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(PDS_BASE,PDS_CLKPLL_TOP_CTRL);
tmpVal = BL_CLR_REG_BIT(tmpVal,PDS_CLKPLL_REFCLK_SEL);
tmpVal = BL_SET_REG_BIT(tmpVal,PDS_CLKPLL_XTAL_RC32M_SEL);
BL_WR_REG(PDS_BASE,PDS_CLKPLL_TOP_CTRL,tmpVal);
return SUCCESS;
}
#endif
@ -425,12 +425,12 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(PDS_BASE,PDS_CLKPLL_TOP_CTRL);
tmpVal = BL_SET_REG_BIT(tmpVal,PDS_CLKPLL_REFCLK_SEL);
tmpVal = BL_CLR_REG_BIT(tmpVal,PDS_CLKPLL_XTAL_RC32M_SEL);
BL_WR_REG(PDS_BASE,PDS_CLKPLL_TOP_CTRL,tmpVal);
return SUCCESS;
}
#endif
@ -448,31 +448,31 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
{
uint32_t tmpVal = 0;
/* Check parameter*/
CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType));
/**************************/
/* select PLL XTAL source */
/**************************/
if((xtalType==PDS_PLL_XTAL_RC32M)||(xtalType==PDS_PLL_XTAL_NONE)){
PDS_Trim_RC32M();
PDS_Select_RC32M_As_PLL_Ref();
}else{
PDS_Select_XTAL_As_PLL_Ref();
}
/*******************************************/
/* PLL power down first, not indispensable */
/*******************************************/
/* power off PLL first, this step is not indispensable */
PDS_Power_Off_PLL();
/********************/
/* PLL param config */
/********************/
/* clkpll_icp_1u */
/* clkpll_icp_5u */
/* clkpll_int_frac_sw */
@ -487,7 +487,7 @@ BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_INT_FRAC_SW,0);
}
BL_WR_REG(PDS_BASE,PDS_CLKPLL_CP,tmpVal);
/* clkpll_c3 */
/* clkpll_cz */
/* clkpll_rz */
@ -507,14 +507,14 @@ BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
}
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_R4,2);
BL_WR_REG(PDS_BASE,PDS_CLKPLL_RZ,tmpVal);
/* clkpll_refdiv_ratio */
/* clkpll_postdiv */
tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_TOP_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_POSTDIV,0x14);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_REFDIV_RATIO,2);
BL_WR_REG(PDS_BASE,PDS_CLKPLL_TOP_CTRL,tmpVal);
/* clkpll_sdmin */
tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_SDM);
switch(xtalType){
@ -544,31 +544,31 @@ BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
break;
}
BL_WR_REG(PDS_BASE,PDS_CLKPLL_SDM,tmpVal);
/* clkpll_sel_fb_clk */
/* clkpll_sel_sample_clk can be 0/1, default is 1 */
tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_FBDV);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SEL_FB_CLK,1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SEL_SAMPLE_CLK,1);
BL_WR_REG(PDS_BASE,PDS_CLKPLL_FBDV,tmpVal);
/*************************/
/* PLL power up sequence */
/*************************/
/* pu_clkpll_sfreg=1 */
tmpVal=BL_RD_REG(PDS_BASE,PDS_PU_RST_CLKPLL);
tmpVal=BL_SET_REG_BIT(tmpVal,PDS_PU_CLKPLL_SFREG);
BL_WR_REG(PDS_BASE,PDS_PU_RST_CLKPLL,tmpVal);
BL602_Delay_US(5);
/* pu_clkpll=1 */
tmpVal=BL_RD_REG(PDS_BASE,PDS_PU_RST_CLKPLL);
tmpVal=BL_SET_REG_BIT(tmpVal,PDS_PU_CLKPLL);
BL_WR_REG(PDS_BASE,PDS_PU_RST_CLKPLL,tmpVal);
/* clkpll_pu_cp=1 */
/* clkpll_pu_pfd=1 */
/* clkpll_pu_fbdv=1 */
@ -579,9 +579,9 @@ BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
tmpVal=BL_SET_REG_BIT(tmpVal,PDS_CLKPLL_PU_FBDV);
tmpVal=BL_SET_REG_BIT(tmpVal,PDS_CLKPLL_PU_POSTDIV);
BL_WR_REG(PDS_BASE,PDS_PU_RST_CLKPLL,tmpVal);
BL602_Delay_US(5);
/* clkpll_sdm_reset=1 */
tmpVal=BL_RD_REG(PDS_BASE,PDS_PU_RST_CLKPLL);
tmpVal=BL_SET_REG_BIT(tmpVal,PDS_CLKPLL_SDM_RESET);
@ -601,7 +601,7 @@ BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
tmpVal=BL_RD_REG(PDS_BASE,PDS_PU_RST_CLKPLL);
tmpVal=BL_CLR_REG_BIT(tmpVal,PDS_CLKPLL_SDM_RESET);
BL_WR_REG(PDS_BASE,PDS_PU_RST_CLKPLL,tmpVal);
return SUCCESS;
}
#endif
@ -631,11 +631,11 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_OUTPUT_EN);
tmpVal |= 0x1FF;
BL_WR_REG(PDS_BASE,PDS_CLKPLL_OUTPUT_EN,tmpVal);
return SUCCESS;
}
#endif
@ -653,11 +653,11 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_OUTPUT_EN);
tmpVal &= (~0x1FF);
BL_WR_REG(PDS_BASE,PDS_CLKPLL_OUTPUT_EN,tmpVal);
return SUCCESS;
}
#endif
@ -675,14 +675,14 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
{
uint32_t tmpVal = 0;
/* Check parameter*/
CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_OUTPUT_EN);
tmpVal |= (1<<pllClk);
BL_WR_REG(PDS_BASE,PDS_CLKPLL_OUTPUT_EN,tmpVal);
return SUCCESS;
}
#endif
@ -700,14 +700,14 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
{
uint32_t tmpVal = 0;
/* Check parameter*/
CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_OUTPUT_EN);
tmpVal &= (~(1<<pllClk));
BL_WR_REG(PDS_BASE,PDS_CLKPLL_OUTPUT_EN,tmpVal);
return SUCCESS;
}
#endif
@ -725,14 +725,14 @@ __WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void)
{
uint32_t tmpVal = 0;
/* pu_clkpll_sfreg=0 */
/* pu_clkpll=0 */
tmpVal=BL_RD_REG(PDS_BASE,PDS_PU_RST_CLKPLL);
tmpVal=BL_CLR_REG_BIT(tmpVal,PDS_PU_CLKPLL_SFREG);
tmpVal=BL_CLR_REG_BIT(tmpVal,PDS_PU_CLKPLL);
BL_WR_REG(PDS_BASE,PDS_PU_RST_CLKPLL,tmpVal);
/* clkpll_pu_cp=0 */
/* clkpll_pu_pfd=0 */
/* clkpll_pu_fbdv=0 */
@ -743,7 +743,7 @@ BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void)
tmpVal=BL_CLR_REG_BIT(tmpVal,PDS_CLKPLL_PU_FBDV);
tmpVal=BL_CLR_REG_BIT(tmpVal,PDS_CLKPLL_PU_POSTDIV);
BL_WR_REG(PDS_BASE,PDS_PU_RST_CLKPLL,tmpVal);
return SUCCESS;
}
#endif
@ -764,7 +764,7 @@ void __IRQ PDS_WAKEUP_IRQHandler(void)
pdsIntCbfArra[intType][0]();
}
}
PDS_IntClear();
}
#endif

12
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_pwm.c
View File

@ -108,14 +108,14 @@ static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph)
uint32_t timeoutCnt = PWM_INT_TIMEOUT_COUNT;
/* Get channel register */
uint32_t PWMx = PWM_BASE;
for (i = 0; i < PWM_CH_MAX; i++) {
tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i)) != 0) {
/* Clear interrupt */
tmpVal |= (1 << (i + PWM_INT_CLEAR_POS));
BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);
/* FIXME: we need set pwm_int_clear to 0 by software and
/* FIXME: we need set pwm_int_clear to 0 by software and
before this,we must make sure pwm_interrupt_sts is 0*/
do{
tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
@ -124,7 +124,7 @@ static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph)
break;
}
}while(BL_GET_REG_BITS_VAL(tmpVal,PWM_INTERRUPT_STS)&(1 << i));
tmpVal &= (~(1 << (i + PWM_INT_CLEAR_POS)));
BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);
if (PWMIntCbfArra[i*PWM_INT_ALL + PWM_INT_PULSE_CNT] != NULL) {
@ -191,7 +191,7 @@ BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg)
tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT);
BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, chCfg->intPulseCnt));
PWM_IntMask(chCfg->ch,PWM_INT_PULSE_CNT,chCfg->intPulseCnt!=0?UNMASK:MASK);
return SUCCESS;
}
@ -236,7 +236,7 @@ void PWM_Channel_Set_Div(uint8_t ch, uint16_t div)
/* Check the parameters */
CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
BL_WR_REG(PWMx, PWM_CLKDIV, div);
}
@ -374,7 +374,7 @@ void PWM_Channel_Disable(uint8_t ch)
/* Config pwm clock to disable pwm */
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
PWM_IntMask(ch,PWM_INT_PULSE_CNT,MASK);
PWM_IntMask(ch,PWM_INT_PULSE_CNT,MASK);
}
/****************************************************************************//**

8
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_romdriver.c
View File

@ -33,7 +33,7 @@
*
******************************************************************************
*/
#include "bl602_romdriver.h"
#include <string.h>
@ -60,14 +60,14 @@
/** @defgroup ROMDRIVER_Private_Variables
* @{
*/
*/
/*@} end of group ROMDRIVER_Private_Variables */
/** @defgroup ROMDRIVER_Global_Variables
* @{
*/
*/
uint32_t const romDriverTable[]={
0x06020002,

8
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_sec_dbg.c
View File

@ -90,10 +90,10 @@
void Sec_Dbg_Read_Chip_ID(uint8_t id[8])
{
uint32_t idLow,idHigh;
idLow=BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_CHIP_ID_LOW);
BL_WRWD_TO_BYTEP(id,idLow);
idHigh=BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_CHIP_ID_HIGH);
BL_WRWD_TO_BYTEP((id+4),idHigh);
}
@ -109,10 +109,10 @@ void Sec_Dbg_Read_Chip_ID(uint8_t id[8])
void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6])
{
uint32_t macLow,macHigh;
macLow=BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_WIFI_MAC_LOW);
BL_WRWD_TO_BYTEP(macAddr,macLow);
macHigh=BL_RD_REG(SEC_DBG_BASE,SEC_DBG_SD_WIFI_MAC_HIGH);
macAddr[4]=(macHigh>>0)&0xff;
macAddr[5]=(macHigh>>8)&0xff;

8
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_sf_ctrl.c
View File

@ -551,7 +551,7 @@ void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region,uint8_t *iv,uint32_t add
/* Do flash key eco*/
uint32_t regionRegBase=SF_Ctrl_Get_AES_Region(SF_CTRL_BASE,!region);
uint32_t tmpVal,i=3;
if(iv!=NULL){
tmpVal=SF_CTRL_SF_AES_IV_W3_OFFSET;
while(i--){
@ -588,7 +588,7 @@ void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region,uint8_t *iv,uint32_t
/* Do flash key eco*/
uint32_t regionRegBase=SF_Ctrl_Get_AES_Region(SF_CTRL_BASE,!region);
uint32_t tmpVal,i=3;
if(iv!=NULL){
tmpVal=SF_CTRL_SF_AES_IV_W0_OFFSET;
while(i--){
@ -765,7 +765,7 @@ void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg)
tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_CMD_EN);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_CMD_BYTE,0);
/* Configure address */
/* Configure address */
if(cfg->addrSize != 0){
tmpVal=BL_SET_REG_BIT(tmpVal,SF_CTRL_SF_IF_0_ADR_EN);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_0_ADR_BYTE,cfg->addrSize-1);
@ -884,7 +884,7 @@ void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdVa
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_CMD_BYTE,0);
}
/* Configure address */
/* Configure address */
if(cfg->addrSize != 0){
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_ADR_EN,1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SF_CTRL_SF_IF_1_ADR_BYTE,cfg->addrSize-1);

14
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_sflash.c
View File

@ -377,7 +377,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg)
if(stat!=SUCCESS){
return stat;
}
if(((uint32_t)&flashCmd)%4==0){
BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4);
}else{
@ -416,7 +416,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg,ui
{
uint32_t cnt=0;
SF_Ctrl_Cmd_Cfg_Type flashCmd;
BL_Err_Type stat=SFlash_Write_Enable(flashCfg);
if(stat!=SUCCESS){
return stat;
@ -463,7 +463,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg,uin
if(stat!=SUCCESS){
return stat;
}
if(((uint32_t)&flashCmd)%4==0){
BL602_MemSet4((uint32_t *)&flashCmd,0,sizeof(flashCmd)/4);
}else{
@ -622,7 +622,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg,
flashCmd.addrSize=3;
for(i=0;i<len;){
/* Write enable is needed for every program */
stat=SFlash_Write_Enable(flashCfg);
if(stat!=SUCCESS){
@ -1085,7 +1085,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg,
}else{
flashCmd.cmdBuf[1]=((!flashCfg->cReadMode)<<24);
}
}
}
flashCmd.addrSize++;
}
}
@ -1172,7 +1172,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable)
tmpVal=BL_CLR_REG_BIT(tmpVal,L1C_WAY_DIS);
tmpVal=BL_SET_REG_BIT(tmpVal,L1C_CNT_EN);
BL_WR_REG(L1C_BASE,L1C_CONFIG,tmpVal);
tmpVal|=(wayDisable<<L1C_WAY_DIS_POS);
/* If way disable is 0x0f, cacheable can't be set */
if(wayDisable!=0x0f){
@ -1357,7 +1357,7 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg,
}else{
flashCmd.cmdBuf[1]=((!flashCfg->cReadMode)<<24);
}
}
}
flashCmd.addrSize++;
}
}

282
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_spi.c
View File

@ -102,11 +102,11 @@ static void SPI_IntHandler(SPI_ID_Type spiNo)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
tmpVal = BL_RD_REG(SPIx,SPI_INT_STS);
/* Transfer end interrupt,shared by both master and slave mode */
if(BL_IS_REG_BIT_SET(tmpVal,SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal,SPI_CR_SPI_END_MASK)){
BL_WR_REG(SPIx,SPI_INT_STS,BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_END_CLR));
@ -169,14 +169,14 @@ BL_Err_Type SPI_Init(SPI_ID_Type spiNo,SPI_CFG_Type* spiCfg)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod));
CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence));
CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence));
CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv));
CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity));
/* spi config */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_DEG_EN,spiCfg->deglitchEnable);
@ -187,7 +187,7 @@ BL_Err_Type SPI_Init(SPI_ID_Type spiNo,SPI_CFG_Type* spiCfg)
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_SCLK_POL,spiCfg->clkPolarity);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,spiCfg->frameSize);
BL_WR_REG(SPIx,SPI_CONFIG,tmpVal);
return SUCCESS;
}
@ -203,11 +203,11 @@ BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo)
{
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
if(SPI_ID_0 == spiNo){
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SPI);
}
return SUCCESS;
}
@ -225,10 +225,10 @@ BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo,SPI_ClockCfg_Type *clockCfg)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Configure length of data phase1/0 and start/stop condition */
tmpVal = BL_RD_REG(SPIx,SPI_PRD_0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_S,clockCfg->startLen-1);
@ -236,11 +236,11 @@ BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo,SPI_ClockCfg_Type *clockCfg)
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_D_PH_0,clockCfg->dataPhase0Len-1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_D_PH_1,clockCfg->dataPhase1Len-1);
BL_WR_REG(SPIx,SPI_PRD_0,tmpVal);
/* Configure length of interval between frame */
tmpVal = BL_RD_REG(SPIx,SPI_PRD_1);
BL_WR_REG(SPIx,SPI_PRD_1,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_PRD_I,clockCfg->intervalLen-1));
return SUCCESS;
}
@ -257,22 +257,22 @@ BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo,SPI_FifoCfg_Type *fifoCfg)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Set fifo threshold value */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_TX_FIFO_TH,fifoCfg->txFifoThreshold-1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_RX_FIFO_TH,fifoCfg->rxFifoThreshold-1);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_1,tmpVal);
/* Enable or disable dma function */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_DMA_TX_EN,fifoCfg->txFifoDmaEnable);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_DMA_RX_EN,fifoCfg->rxFifoDmaEnable);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
return SUCCESS;
}
@ -289,10 +289,10 @@ BL_Err_Type SPI_Enable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType));
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
if(modeType != SPI_WORK_MODE_SLAVE){
/* master mode */
@ -304,7 +304,7 @@ BL_Err_Type SPI_Enable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType)
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_S_EN);
}
BL_WR_REG(SPIx,SPI_CONFIG,tmpVal);
return SUCCESS;
}
@ -321,16 +321,16 @@ BL_Err_Type SPI_Disable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType));
/* close master and slave */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
tmpVal = BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_M_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_S_EN);
BL_WR_REG(SPIx,SPI_CONFIG,tmpVal);
return SUCCESS;
}
@ -347,13 +347,13 @@ BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo,uint16_t value)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Set time-out value */
tmpVal = BL_RD_REG(SPIx,SPI_STO_VALUE);
BL_WR_REG(SPIx,SPI_STO_VALUE,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_STO_VALUE,value-1));
return SUCCESS;
}
@ -373,12 +373,12 @@ BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo,uint8_t cnt)
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Set count value */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_DEG_CNT,cnt-1);
BL_WR_REG(SPIx,SPI_CONFIG,tmpVal);
return SUCCESS;
}
@ -396,18 +396,18 @@ BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo,uint8_t startPoint,uint8_t stop
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Enable rx ignore function */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Set start and stop point */
tmpVal = startPoint<<SPI_CR_SPI_RXD_IGNR_S_POS | stopPoint;
BL_WR_REG(SPIx,SPI_RXD_IGNR,tmpVal);
return SUCCESS;
}
@ -423,14 +423,14 @@ BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Disable rx ignore function */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
return SUCCESS;
}
@ -446,14 +446,14 @@ BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Clear tx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR));
return SUCCESS;
}
@ -469,14 +469,14 @@ BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Clear rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR));
return SUCCESS;
}
@ -493,10 +493,10 @@ BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo,SPI_INT_Type intType)
{
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Clear certain or all interrupt */
tmpVal = BL_RD_REG(SPIx,SPI_INT_STS);
if(SPI_INT_ALL == intType){
@ -505,7 +505,7 @@ BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo,SPI_INT_Type intType)
tmpVal |= 1<<(intType+SPI_CR_SPI_END_CLR_POS);
}
BL_WR_REG(SPIx,SPI_INT_STS,tmpVal);
return SUCCESS;
}
@ -545,10 +545,10 @@ BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo,SPI_INT_Type intType,BL_Mask_Type intM
tmpVal &= ~(1<<(intType+SPI_CR_SPI_END_MASK_POS));
}
}
/* Write back */
BL_WR_REG(SPIx,SPI_INT_STS,tmpVal);
return SUCCESS;
}
@ -569,7 +569,7 @@ BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo,SPI_INT_Type intType,intC
CHECK_PARAM(IS_SPI_INT_TYPE(intType));
spiIntCbfArra[spiNo][intType] = cbFun;
return SUCCESS;
}
@ -585,13 +585,13 @@ BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo,SPI_INT_Type intType,intC
BL_Err_Type SPI_SendData(SPI_ID_Type spiNo,uint32_t data)
{
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Write tx fifo */
BL_WR_REG(SPIx,SPI_FIFO_WDATA,data);
return SUCCESS;
}
@ -612,29 +612,29 @@ BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo,uint8_t *buff,uint32_t length,SPI_T
uint32_t txLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,0));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Send 8-bit datas */
for(txLen=0;txLen<length;txLen++){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,(uint32_t)buff[txLen]);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -646,7 +646,7 @@ BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo,uint8_t *buff,uint32_t length,SPI_T
}
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_RDATA);
}
return SUCCESS;
}
@ -667,29 +667,29 @@ BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo,uint16_t *buff,uint32_t length,SPI
uint32_t txLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,1));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Send 16-bit datas */
for(txLen=0;txLen<length;txLen++){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,(uint32_t)buff[txLen]);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -701,7 +701,7 @@ BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo,uint16_t *buff,uint32_t length,SPI
}
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_RDATA);
}
return SUCCESS;
}
@ -722,29 +722,29 @@ BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI
uint32_t txLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,2));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Send 24-bit datas */
for(txLen=0;txLen<length;txLen++){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,buff[txLen]);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -756,7 +756,7 @@ BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI
}
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_RDATA);
}
return SUCCESS;
}
@ -777,29 +777,29 @@ BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI
uint32_t txLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,3));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Send 32-bit datas */
for(txLen=0;txLen<length;txLen++){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,buff[txLen]);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -811,7 +811,7 @@ BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI
}
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_RDATA);
}
return SUCCESS;
}
@ -832,29 +832,29 @@ BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo,uint8_t *buff,uint32_t length,SPI_T
uint32_t rxLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,0));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Receive 8-bit datas */
while(rxLen<length){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,0);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -866,7 +866,7 @@ BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo,uint8_t *buff,uint32_t length,SPI_T
}
buff[rxLen++] = (uint8_t)(BL_RD_REG(SPIx,SPI_FIFO_RDATA)&0xff);
}
return SUCCESS;
}
@ -887,29 +887,29 @@ BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo,uint16_t *buff,uint32_t length,SPI
uint32_t rxLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,1));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Receive 16-bit datas */
while(rxLen<length){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,0);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -921,7 +921,7 @@ BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo,uint16_t *buff,uint32_t length,SPI
}
buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx,SPI_FIFO_RDATA)&0xffff);
}
return SUCCESS;
}
@ -942,29 +942,29 @@ BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI
uint32_t rxLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,2));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Receive 24-bit datas */
while(rxLen<length){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,0);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -976,7 +976,7 @@ BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI
}
buff[rxLen++] = BL_RD_REG(SPIx,SPI_FIFO_RDATA)&0xffffff;
}
return SUCCESS;
}
@ -997,29 +997,29 @@ BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI
uint32_t rxLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,3));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Receive 32-bit datas */
while(rxLen<length){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,0);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -1031,7 +1031,7 @@ BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI
}
buff[rxLen++] = BL_RD_REG(SPIx,SPI_FIFO_RDATA);
}
return SUCCESS;
}
@ -1053,29 +1053,29 @@ BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo,uint8_t *sendBuff,uint8_t *recv
uint32_t txLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,0));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Send and receive 8-bit datas */
for(txLen=0;txLen<length;txLen++){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,(uint32_t)sendBuff[txLen]);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -1087,7 +1087,7 @@ BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo,uint8_t *sendBuff,uint8_t *recv
}
recvBuff[txLen] = (uint8_t)(BL_RD_REG(SPIx,SPI_FIFO_RDATA)&0xff);
}
return SUCCESS;
}
@ -1109,29 +1109,29 @@ BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo,uint16_t *sendBuff,uint16_t *r
uint32_t txLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,1));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Send and receive 16-bit datas */
for(txLen=0;txLen<length;txLen++){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,(uint32_t)sendBuff[txLen]);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -1143,7 +1143,7 @@ BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo,uint16_t *sendBuff,uint16_t *r
}
recvBuff[txLen] = (uint16_t)(BL_RD_REG(SPIx,SPI_FIFO_RDATA)&0xffff);
}
return SUCCESS;
}
@ -1165,29 +1165,29 @@ BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *r
uint32_t txLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,2));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Send and receive 24-bit datas */
for(txLen=0;txLen<length;txLen++){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,sendBuff[txLen]);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -1199,7 +1199,7 @@ BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *r
}
recvBuff[txLen] = BL_RD_REG(SPIx,SPI_FIFO_RDATA)&0xffffff;
}
return SUCCESS;
}
@ -1221,29 +1221,29 @@ BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *r
uint32_t txLen = 0;
uint32_t SPIx = spiAddr[spiNo];
uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));
/* Set valid width for each fifo entry */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,SPI_CR_SPI_FRAME_SIZE,3));
/* Disable rx ignore */
tmpVal = BL_RD_REG(SPIx,SPI_CONFIG);
BL_WR_REG(SPIx,SPI_CONFIG,BL_CLR_REG_BIT(tmpVal,SPI_CR_SPI_RXD_IGNR_EN));
/* Clear tx and rx fifo */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_RX_FIFO_CLR);
BL_WR_REG(SPIx,SPI_FIFO_CONFIG_0,tmpVal);
/* Send and receive 32-bit datas */
for(txLen=0;txLen<length;txLen++){
BL_WR_REG(SPIx,SPI_FIFO_WDATA,sendBuff[txLen]);
timeoutCnt = SPI_RX_TIMEOUT_COUNT;
while(SPI_GetRxFifoCount(spiNo) == 0){
if(timeoutType){
@ -1255,7 +1255,7 @@ BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *r
}
recvBuff[txLen] = BL_RD_REG(SPIx,SPI_FIFO_RDATA);
}
return SUCCESS;
}
@ -1270,10 +1270,10 @@ BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *r
uint32_t SPI_ReceiveData(SPI_ID_Type spiNo)
{
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
return BL_RD_REG(SPIx,SPI_FIFO_RDATA);
}
@ -1288,10 +1288,10 @@ uint32_t SPI_ReceiveData(SPI_ID_Type spiNo)
uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo)
{
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Get count value */
return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx,SPI_FIFO_CONFIG_1),SPI_TX_FIFO_CNT);
}
@ -1307,10 +1307,10 @@ uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo)
uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo)
{
uint32_t SPIx = spiAddr[spiNo];
/* Check the parameters */
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Get count value */
return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx,SPI_FIFO_CONFIG_1),SPI_RX_FIFO_CNT);
}
@ -1369,7 +1369,7 @@ BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo)
CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
/* Get bus busy status */
tmpVal = BL_RD_REG(SPIx,SPI_BUS_BUSY);
tmpVal = BL_RD_REG(SPIx,SPI_BUS_BUSY);
if(BL_IS_REG_BIT_SET(tmpVal,SPI_STS_SPI_BUS_BUSY)){
return SET;
}else{
@ -1396,7 +1396,7 @@ BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo,SPI_FifoStatus_Type fifoSts)
CHECK_PARAM(IS_SPI_FIFOSTATUS_TYPE(fifoSts));
/* Get tx/rx fifo overflow or underflow status */
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
tmpVal = BL_RD_REG(SPIx,SPI_FIFO_CONFIG_0);
if((tmpVal&(1U<<(fifoSts+SPI_TX_FIFO_OVERFLOW_POS))) !=0){
return SET;
}else{

2
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_timer.c
View File

@ -302,7 +302,7 @@ void TIMER_SetPreloadTrigSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type pl
*
*******************************************************************************/
void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode)
{
{
uint32_t tmpval;
/* Check the parameters */

62
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_tzc_sec.c
View File

@ -90,11 +90,11 @@
void TZC_Sboot_Set(uint8_t Val)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_SBOOT_DONE,Val);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal);
}
@ -111,24 +111,24 @@ void TZC_Sboot_Set(uint8_t Val)
void TZC_Set_Rom0_R0_Protect(uint32_t start,uint32_t end)
{
uint32_t tmpVal;
/* Set Range */
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM0_R0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_START,start>>10);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_END,end>>10);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM0_R0,tmpVal);
/* Enable */
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_ID0_EN,0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_ID1_EN,0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_EN,1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R0_LOCK,1);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal);
}
@ -145,24 +145,24 @@ void TZC_Set_Rom0_R0_Protect(uint32_t start,uint32_t end)
void TZC_Set_Rom0_R1_Protect(uint32_t start,uint32_t end)
{
uint32_t tmpVal;
/* Set Range */
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM0_R1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_START,start>>10);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_END,end>>10);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM0_R1,tmpVal);
/* Enable */
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_ID0_EN,0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_ID1_EN,0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_EN,1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM0_R1_LOCK,1);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal);
}
@ -179,24 +179,24 @@ void TZC_Set_Rom0_R1_Protect(uint32_t start,uint32_t end)
void TZC_Set_Rom1_R0_Protect(uint32_t start,uint32_t end)
{
uint32_t tmpVal;
/* Set Range */
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM1_R0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_START,start>>10);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_END,end>>10);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM1_R0,tmpVal);
/* Enable */
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_ID0_EN,0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_ID1_EN,0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_EN,1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R0_LOCK,1);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal);
}
@ -213,24 +213,24 @@ void TZC_Set_Rom1_R0_Protect(uint32_t start,uint32_t end)
void TZC_Set_Rom1_R1_Protect(uint32_t start,uint32_t end)
{
uint32_t tmpVal;
/* Set Range */
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM1_R1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_START,start>>10);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_END,end>>10);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM1_R1,tmpVal);
/* Enable */
tmpVal=BL_RD_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_ID0_EN,0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_ID1_EN,0);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_EN,1);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,TZC_SEC_TZC_ROM1_R1_LOCK,1);
BL_WR_REG(TZC_SEC_BASE,TZC_SEC_TZC_ROM_CTRL,tmpVal);
}

132
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_uart.c
View File

@ -113,7 +113,7 @@ static void UART_IntHandler(UART_ID_Type uartId)
uartIntCbfArra[uartId][UART_INT_TX_END]();
}
}
/* Length of uart rx data transfer arrived interrupt */
if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_END_MASK)){
BL_WR_REG(UARTx,UART_INT_CLEAR,0x2);
@ -121,21 +121,21 @@ static void UART_IntHandler(UART_ID_Type uartId)
uartIntCbfArra[uartId][UART_INT_RX_END]();
}
}
/* Tx fifo ready interrupt,auto-cleared when data is pushed */
if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_FIFO_MASK)){
if(uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL){
uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ]();
}
}
/* Rx fifo ready interrupt,auto-cleared when data is popped */
if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_FIFO_MASK)){
if(uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL){
uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ]();
}
}
/* Rx time-out interrupt */
if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_RTO_MASK)){
BL_WR_REG(UARTx,UART_INT_CLEAR,0x10);
@ -143,7 +143,7 @@ static void UART_IntHandler(UART_ID_Type uartId)
uartIntCbfArra[uartId][UART_INT_RTO]();
}
}
/* Rx parity check error interrupt */
if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_PCE_MASK)){
BL_WR_REG(UARTx,UART_INT_CLEAR,0x20);
@ -151,14 +151,14 @@ static void UART_IntHandler(UART_ID_Type uartId)
uartIntCbfArra[uartId][UART_INT_PCE]();
}
}
/* Tx fifo overflow/underflow error interrupt */
if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_FER_MASK)){
if(uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL){
uartIntCbfArra[uartId][UART_INT_TX_FER]();
}
}
/* Rx fifo overflow/underflow error interrupt */
if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_FER_MASK)){
if(uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL){
@ -191,24 +191,24 @@ BL_Err_Type UART_Init(UART_ID_Type uartId,UART_CFG_Type* uartCfg)
uint32_t fraction = 0;
uint32_t baudRateDivisor = 0;
uint32_t UARTx = uartAddr[uartId];
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity));
CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits));
CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits));
CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse));
/* Cal the baud rate divisor */
fraction = uartCfg->uartClk * 10 / uartCfg->baudRate % 10;
baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate;
if(fraction >= 5){
++baudRateDivisor;
}
/* Set the baud rate register value */
BL_WR_REG(UARTx,UART_BIT_PRD,((baudRateDivisor-1)<<0x10)|((baudRateDivisor-1)&0xFFFF));
/* Configure parity type */
tmpValTxCfg = BL_RD_REG(UARTx,UART_UTX_CONFIG);
tmpValRxCfg = BL_RD_REG(UARTx,UART_URX_CONFIG);
@ -233,39 +233,39 @@ BL_Err_Type UART_Init(UART_ID_Type uartId,UART_CFG_Type* uartCfg)
default:
break;
}
/* Configure data bits */
tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg,UART_CR_UTX_BIT_CNT_D,(uartCfg->dataBits+4));
tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg,UART_CR_URX_BIT_CNT_D,(uartCfg->dataBits+4));
/* Configure tx stop bits */
tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg,UART_CR_UTX_BIT_CNT_P,(uartCfg->stopBits+1));
/* Configure tx cts flow control function */
if(ENABLE == uartCfg->ctsFlowControl){
tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg,UART_CR_UTX_CTS_EN);
}else{
tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg,UART_CR_UTX_CTS_EN);
}
/* Configure rx input de-glitch function */
if(ENABLE == uartCfg->rxDeglitch){
tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg,UART_CR_URX_DEG_EN);
}else{
tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg,UART_CR_URX_DEG_EN);
}
/* Configure rx rts output SW control mode */
if(ENABLE == uartCfg->rtsSoftwareControl){
tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg,UART_CR_URX_RTS_SW_MODE);
}else{
tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg,UART_CR_URX_RTS_SW_MODE);
}
/* Write back */
BL_WR_REG(UARTx,UART_UTX_CONFIG,tmpValTxCfg);
BL_WR_REG(UARTx,UART_URX_CONFIG,tmpValRxCfg);
/* Configure LSB-first or MSB-first */
tmpValTxCfg = BL_RD_REG(UARTx,UART_DATA_CONFIG);
if(UART_MSB_FIRST == uartCfg->byteBitInverse){
@ -274,7 +274,7 @@ BL_Err_Type UART_Init(UART_ID_Type uartId,UART_CFG_Type* uartCfg)
tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg,UART_CR_UART_BIT_INV);
}
BL_WR_REG(UARTx,UART_DATA_CONFIG,tmpValTxCfg);
return SUCCESS;
}
@ -293,7 +293,7 @@ BL_Err_Type UART_DeInit(UART_ID_Type uartId)
}else if(UART1_ID==uartId){
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
}
return SUCCESS;
}
@ -310,10 +310,10 @@ BL_Err_Type UART_FifoConfig(UART_ID_Type uartId,UART_FifoCfg_Type* fifoCfg)
{
uint32_t tmpVal = 0;
uint32_t UARTx = uartAddr[uartId];
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Deal with uart fifo configure register */
tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_1);
/* Configure dma tx fifo threshold */
@ -322,7 +322,7 @@ BL_Err_Type UART_FifoConfig(UART_ID_Type uartId,UART_FifoCfg_Type* fifoCfg)
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,UART_RX_FIFO_TH,fifoCfg->rxFifoDmaThreshold-1);
/* Write back */
BL_WR_REG(UARTx,UART_FIFO_CONFIG_1,tmpVal);
/* Enable or disable uart fifo dma function */
tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_0);
if(ENABLE == fifoCfg->txFifoDmaEnable){
@ -336,7 +336,7 @@ BL_Err_Type UART_FifoConfig(UART_ID_Type uartId,UART_FifoCfg_Type* fifoCfg)
tmpVal = BL_CLR_REG_BIT(tmpVal,UART_DMA_RX_EN);
}
BL_WR_REG(UARTx,UART_FIFO_CONFIG_0,tmpVal);
return SUCCESS;
}
@ -353,10 +353,10 @@ BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type* irCfg)
{
uint32_t tmpVal = 0;
uint32_t UARTx = uartAddr[uartId];
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Configure tx ir mode */
tmpVal = BL_RD_REG(UARTx,UART_UTX_CONFIG);
if(ENABLE == irCfg->txIrEnable){
@ -370,7 +370,7 @@ BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type* irCfg)
tmpVal = BL_CLR_REG_BIT(tmpVal,UART_CR_UTX_IR_INV);
}
BL_WR_REG(UARTx,UART_UTX_CONFIG,tmpVal);
/* Configure rx ir mode */
tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG);
if(ENABLE == irCfg->rxIrEnable){
@ -384,13 +384,13 @@ BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type* irCfg)
tmpVal = BL_CLR_REG_BIT(tmpVal,UART_CR_URX_IR_INV);
}
BL_WR_REG(UARTx,UART_URX_CONFIG,tmpVal);
/* Configure tx ir pulse start and stop position */
BL_WR_REG(UARTx,UART_UTX_IR_POSITION,irCfg->txIrPulseStop<<0x10|irCfg->txIrPulseStart);
/* Configure rx ir pulse start position */
BL_WR_REG(UARTx,UART_URX_IR_POSITION,irCfg->rxIrPulseStart);
return SUCCESS;
}
@ -423,7 +423,7 @@ BL_Err_Type UART_Enable(UART_ID_Type uartId,UART_Direction_Type direct)
tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG);
BL_WR_REG(UARTx,UART_URX_CONFIG,BL_SET_REG_BIT(tmpVal,UART_CR_URX_EN));
}
return SUCCESS;
}
@ -456,7 +456,7 @@ BL_Err_Type UART_Disable(UART_ID_Type uartId,UART_Direction_Type direct)
tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG);
BL_WR_REG(UARTx,UART_URX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_URX_EN));
}
return SUCCESS;
}
@ -477,11 +477,11 @@ BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId,uint16_t length)
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Set length */
tmpVal = BL_RD_REG(UARTx,UART_UTX_CONFIG);
BL_WR_REG(UARTx,UART_UTX_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,UART_CR_UTX_LEN,length-1));
return SUCCESS;
}
@ -502,11 +502,11 @@ BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId,uint16_t length)
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Set length */
tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG);
BL_WR_REG(UARTx,UART_URX_CONFIG,BL_SET_REG_BITS_VAL(tmpVal,UART_CR_URX_LEN,length-1));
return SUCCESS;
}
@ -526,12 +526,12 @@ BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId,uint8_t time)
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Set time-out value */
tmpVal = BL_RD_REG(UARTx,UART_URX_RTO_TIMER);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,UART_CR_URX_RTO_VALUE,time-1);
BL_WR_REG(UARTx,UART_URX_RTO_TIMER,tmpVal);
return SUCCESS;
}
@ -551,12 +551,12 @@ BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId,uint8_t deglitchCnt)
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Set count value */
tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal,UART_CR_URX_DEG_CNT,deglitchCnt-1);
BL_WR_REG(UARTx,UART_URX_CONFIG,tmpVal);
return SUCCESS;
}
@ -573,16 +573,16 @@ BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId,UART_AutoBaudDetection_Type aut
{
uint32_t UARTx = uartAddr[uartId];
uint16_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Get detection value */
tmpVal = UART_GetAutoBaudCount(uartId,autoBaudDet);
/* Set tx baudrate */
BL_WR_REG(UARTx,UART_BIT_PRD,tmpVal<<0x10 | tmpVal);
return SUCCESS;
}
@ -605,7 +605,7 @@ BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId)
/* Rts set 1*/
tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG);
BL_WR_REG(UARTx,UART_URX_CONFIG,BL_SET_REG_BIT(tmpVal,UART_CR_URX_RTS_SW_VAL));
return SUCCESS;
}
@ -628,7 +628,7 @@ BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId)
/* Rts clear 0 */
tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG);
BL_WR_REG(UARTx,UART_URX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_URX_RTS_SW_VAL));
return SUCCESS;
}
@ -645,10 +645,10 @@ BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId,BL_Fun_Type txFreeRun)
{
uint32_t tmpVal = 0;
uint32_t UARTx = uartAddr[uartId];
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Enable or disable tx free run mode */
tmpVal = BL_RD_REG(UARTx,UART_UTX_CONFIG);
if(ENABLE == txFreeRun){
@ -656,7 +656,7 @@ BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId,BL_Fun_Type txFreeRun)
}else{
BL_WR_REG(UARTx,UART_UTX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_UTX_FRM_EN));
}
return SUCCESS;
}
@ -673,10 +673,10 @@ BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId,BL_Fun_Type autoBaud)
{
uint32_t tmpVal = 0;
uint32_t UARTx = uartAddr[uartId];
/* Check the parameters */
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Enable or disable auto baud rate detection function */
tmpVal = BL_RD_REG(UARTx,UART_URX_CONFIG);
if(ENABLE == autoBaud){
@ -684,7 +684,7 @@ BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId,BL_Fun_Type autoBaud)
}else{
BL_WR_REG(UARTx,UART_URX_CONFIG,BL_CLR_REG_BIT(tmpVal,UART_CR_URX_ABR_EN));
}
return SUCCESS;
}
@ -707,7 +707,7 @@ BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId)
/* Clear tx fifo */
tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_0);
BL_WR_REG(UARTx,UART_FIFO_CONFIG_0,BL_SET_REG_BIT(tmpVal,UART_TX_FIFO_CLR));
return SUCCESS;
}
@ -730,7 +730,7 @@ BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId)
/* Clear rx fifo */
tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_0);
BL_WR_REG(UARTx,UART_FIFO_CONFIG_0,BL_SET_REG_BIT(tmpVal,UART_RX_FIFO_CLR));
return SUCCESS;
}
@ -770,10 +770,10 @@ BL_Err_Type UART_IntMask(UART_ID_Type uartId,UART_INT_Type intType,BL_Mask_Type
tmpVal &= ~(1<<intType);
}
}
/* Write back */
BL_WR_REG(UARTx,UART_INT_MASK,tmpVal);
return SUCCESS;
}
@ -803,10 +803,10 @@ BL_Err_Type UART_IntClear(UART_ID_Type uartId,UART_INT_Type intType)
}else{
tmpVal |= 1<<intType;
}
/* Write back */
BL_WR_REG(UARTx,UART_INT_CLEAR,tmpVal);
return SUCCESS;
}
@ -827,7 +827,7 @@ BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId,UART_INT_Type intType,
CHECK_PARAM(IS_UART_INT_TYPE(intType));
uartIntCbfArra[uartId][intType] = cbFun;
return SUCCESS;
}
@ -862,7 +862,7 @@ BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t* data,uint32_t len)
}
}
}
return SUCCESS;
}
@ -897,9 +897,9 @@ BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t* data,uint32_t len)
}
}
}
while(UART_GetTxBusBusyStatus(uartId) == SET){}
return SUCCESS;
}
@ -925,7 +925,7 @@ uint32_t UART_ReceiveData(UART_ID_Type uartId,uint8_t* data,uint32_t maxLen)
while(rxLen<maxLen && UART_GetRxFifoCount(uartId)>0){
data[rxLen++] = BL_RD_BYTE(UARTx+UART_FIFO_RDATA_OFFSET);
}
return rxLen;
}
@ -1044,7 +1044,7 @@ BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId)
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Get tx bus busy status */
tmpVal = BL_RD_REG(UARTx,UART_STATUS);
tmpVal = BL_RD_REG(UARTx,UART_STATUS);
if(BL_IS_REG_BIT_SET(tmpVal,UART_STS_UTX_BUS_BUSY))
{
return SET;
@ -1070,7 +1070,7 @@ BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId)
CHECK_PARAM(IS_UART_ID_TYPE(uartId));
/* Get rx bus busy status */
tmpVal = BL_RD_REG(UARTx,UART_STATUS);
tmpVal = BL_RD_REG(UARTx,UART_STATUS);
if(BL_IS_REG_BIT_SET(tmpVal,UART_STS_URX_BUS_BUSY))
{
return SET;
@ -1098,7 +1098,7 @@ BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId,UART_Overflow_Type overfl
CHECK_PARAM(IS_UART_OVERFLOW_TYPE(overflow));
/* Get tx/rx fifo overflow or underflow status */
tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_0);
tmpVal = BL_RD_REG(UARTx,UART_FIFO_CONFIG_0);
if((tmpVal&(1U<<(overflow+4))) !=0)
{
return SET;

2
components/bl602/bl602_std/bl602_std/StdDriver/Src/bl602_xip_sflash.c
View File

@ -95,7 +95,7 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg
/* XIP_SFlash_Delay */
volatile uint32_t i=32*2;
while(i--);
SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
/* Exit form continous read for accepting command */
SFlash_Reset_Continue_Read(pFlashCfg);

6
components/bl602/bl602_wifi/include/bl60x_fw_api.h
View File

@ -38,11 +38,11 @@
/* when an error action is taking place the reason code can indicate */
/* what the reason code. */
/*--------------------------------------------------------------------*/
#define WLAN_FW_SUCCESSFUL 0
#define WLAN_FW_TX_AUTH_FRAME_ALLOCATE_FAIILURE 1
#define WLAN_FW_SUCCESSFUL 0
#define WLAN_FW_TX_AUTH_FRAME_ALLOCATE_FAIILURE 1
#define WLAN_FW_AUTHENTICATION_FAIILURE 2
#define WLAN_FW_AUTH_ALGO_FAIILURE 3
#define WLAN_FW_TX_ASSOC_FRAME_ALLOCATE_FAIILURE 4
#define WLAN_FW_TX_ASSOC_FRAME_ALLOCATE_FAIILURE 4
#define WLAN_FW_ASSOCIATE_FAIILURE 5
#define WLAN_FW_DEAUTH_BY_AP_WHEN_NOT_CONNECTION 6
#define WLAN_FW_DEAUTH_BY_AP_WHEN_CONNECTION 7

2
components/bl602/bl602_wifidrv/bl60x_wifi_driver/bl_cmds.c
View File

@ -170,7 +170,7 @@ static void cmd_mgr_print(struct bl_cmd_mgr *cmd_mgr)
list_for_each_entry(cur, &cmd_mgr->cmds, list) {
cmd_dump(cur);
}
os_mutex_give(cmd_mgr->lock);
}

2
components/bl602/bl602_wifidrv/bl60x_wifi_driver/bl_defs.h
View File

@ -35,7 +35,7 @@
#include "bl_cmds.h"
#include "bl_mod_params.h"
#define ETH_ALEN 6
#define ETH_ALEN 6
/**
****************************************************************************************
*

2
components/bl602/bl602_wifidrv/bl60x_wifi_driver/bl_mod_params.c
View File

@ -70,7 +70,7 @@ struct bl_mod_params bl_mod_params = {
// By default, only enable UAPSD for Voice queue (see IEEE80211_DEFAULT_UAPSD_QUEUE comment)
COMMON_PARAM(uapsd_queues, IEEE80211_WMM_IE_STA_QOSINFO_AC_VO, IEEE80211_WMM_IE_STA_QOSINFO_AC_VO)
COMMON_PARAM(tdls, false, false)
/* FULLMAC only parameters */
};

6
components/bl602/bl602_wifidrv/bl60x_wifi_driver/bl_msg_tx.c
View File

@ -166,7 +166,7 @@ static const struct ieee80211_channel bl_channels_24_ER[] = {
{ .band = NL80211_BAND_2GHZ, .center_freq = 2472, .hw_value = 13, .max_power=16},
};
static const struct ieee80211_dot_d country_list[] =
static const struct ieee80211_dot_d country_list[] =
{
{
.code = "CN",
@ -1011,7 +1011,7 @@ int bl_send_cfg_task_req(struct bl_hw *bl_hw, uint32_t ops, uint32_t task, uint3
req->u.set[0].length = utils_tlv_bl_pack_auto(
req->u.set[0].buf,
ENTRY_BUF_SIZE,
type,
type,
arg1
);
}
@ -1062,7 +1062,7 @@ int bl_send_channel_set_req(struct bl_hw *bl_hw, int channel)
param->type = PHY_CHNL_BW_20;
param->prim20_freq = phy_channel_to_freq(param->band, channel);
param->center1_freq = phy_channel_to_freq(param->band, channel);//useless when bandwidth bigger than 20MHZ?
param->center2_freq = phy_channel_to_freq(param->band, channel);//useless when bandwidth bigger than 20MHZ?
param->center2_freq = phy_channel_to_freq(param->band, channel);//useless when bandwidth bigger than 20MHZ?
param->index = 0;
param->tx_power = 15;//FIXME which value should be tx_power set?

2
components/bl602/bl602_wifidrv/bl60x_wifi_driver/bl_utils.c
View File

@ -506,7 +506,7 @@ void bl_utils_dump(void)
txhdr = (struct bl_txhdr*)(((uint32_t)p->payload) + RWNX_HWTXHDR_ALIGN_PADS((uint32_t)p->payload));
printf(" [%lu]%p(%p:%08lX)\r\n",
(ipc_env->txdesc_used_idx + i) & (NX_TXDESC_CNT0 - 1),
p,
p,
p ? (void*)(txhdr->host.status_addr) : 0,
p ? txhdr->status.value : 0
);

2
components/bl602/bl602_wifidrv/bl60x_wifi_driver/errno.h
View File

@ -29,7 +29,7 @@
*/
#ifndef __ERRNO_H__
#define __ERRNO_H__
#define EPERM 1
#define EPERM 1
/**
****************************************************************************************
*

2
components/bl602/bl602_wifidrv/bl60x_wifi_driver/ipc_compat.h
View File

@ -38,7 +38,7 @@
#if 1
#define __WARN() printf("%s:%d\r\n", __func__, __LINE__)
#else
#define __WARN()
#define __WARN()
#endif
#define WARN_ON(condition) ({ \

8
components/bl602/bl602_wifidrv/bl60x_wifi_driver/ipc_host.c
View File

@ -86,7 +86,7 @@ extern int internel_cal_size_tx_hdr;
);
utils_list_init(&tx_list_bl);
#if 0
/**
****************************************************************************************
*
@ -185,7 +185,7 @@ uint32_t ipc_host_get_status(struct ipc_host_env_tag *env)
status = ipc_emb2app_status_get(env->shared);
return status;
}
}
uint32_t ipc_host_get_rawstatus(struct ipc_host_env_tag *env)
{
@ -194,7 +194,7 @@ uint32_t ipc_host_get_rawstatus(struct ipc_host_env_tag *env)
status = ipc_emb2app_rawstatus_get(env->shared);
return status;
}
}
static void ipc_host_msgack_handler(struct ipc_host_env_tag *env)
{
@ -274,7 +274,7 @@ volatile struct txdesc_host *ipc_host_txdesc_get(struct ipc_host_env_tag *env)
uint32_t free_idx = env->txdesc_free_idx;
os_printf("free_idx is %u(%u), used_idx is %u(%u), cnt is %u\r\n",
free_idx,
free_idx,
free_idx & nx_txdesc_cnt_msk[0],
used_idx,
used_idx & nx_txdesc_cnt_msk[0],

8
components/bl602/bl602_wifidrv/bl60x_wifi_driver/lmac_msg.h
View File

@ -1957,7 +1957,7 @@ enum cfg_msg_tag
struct
{
/// TASK
/// TASK
uint32_t task;
/// ELEMENT
uint32_t element;
@ -1974,7 +1974,7 @@ struct cfg_start_req
union {
/// struct for get ELEMENT
struct {
/// TASK
/// TASK
uint32_t task;
/// ELEMENT
uint32_t element;
@ -1982,7 +1982,7 @@ struct cfg_start_req
/// struct for reset ELEMENT
struct {
/// TASK
/// TASK
uint32_t task;
/// ELEMENT
uint32_t element;
@ -1990,7 +1990,7 @@ struct cfg_start_req
/// struct for set ELEMENT with TLV based
struct {
/// TASK
/// TASK
uint32_t task;
/// ELEMENT
uint32_t element;

10
components/bl602/bl602_wifidrv/bl60x_wifi_driver/stateMachine.c
View File

@ -31,19 +31,19 @@
/*
/*
* Copyright (c) 2013 Andreas Misje
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@ -133,7 +133,7 @@ int stateM_handleEvent( struct stateMachine *fsm,
fsm->previousState = fsm->currentState;
fsm->currentState = nextState;
/* If the state returned to itself: */
if ( fsm->currentState == fsm->previousState )
return stateM_stateLoopSelf;

26
components/bl602/bl602_wifidrv/bl60x_wifi_driver/stateMachine.h
View File

@ -31,19 +31,19 @@
/*
/*
* Copyright (c) 2013 Andreas Misje
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@ -117,7 +117,7 @@ struct event
{
/** \brief Type of event. Defined by user. */
int type;
/**
/**
* \brief Event payload.
*
* How this is used is entirely up to the user. This data
@ -212,7 +212,7 @@ struct transition
* \returns true if the event's data fulfils the condition, otherwise false.
*/
bool ( *guard )( void *condition, struct event *event );
/**
/**
* \brief Function containing tasks to be performed during the transition
*
* The transition may optionally do some work in this function before
@ -254,7 +254,7 @@ struct transition
* state has a parent state, the event will be passed to the parent state.
* This behaviour is repeated for all parents. Thus all children of a state
* have a set of common #transitions. A parent state's #entryAction will not
* be called if an event is passed on to a child state.
* be called if an event is passed on to a child state.
*
* The following lists the different types of states that may be created, and
* how to create them:
@ -328,11 +328,11 @@ struct state
* child state that serves as an entry point.
*/
const struct state *entryState;
/**
/**
* \brief An array of transitions for the state.
*/
struct transition *transitions;
/**
/**
* \brief Number of transitions in the #transitions array.
*/
size_t numTransitions;
@ -341,7 +341,7 @@ struct state
* #exitAction, and in any \ref transition::action "transition action"
*/
void *data;
/**
/**
* \brief This function is called whenever the state is being entered. May
* be NULL.
*
@ -377,14 +377,14 @@ struct stateMachine
{
/** \brief Pointer to the current state */
const struct state *currentState;
/**
/**
* \brief Pointer to previous state
*
* The previous state is stored for convenience in case the user needs to
* keep track of previous states.
*/
const struct state *previousState;
/**
/**
* \brief Pointer to a state that will be entered whenever an error occurs
* in the state machine.
*
@ -405,7 +405,7 @@ struct stateMachine
*
* \note The \ref #state::entryAction "entry action" for \pn{initialState}
* will not be called.
*
*
* \note If \pn{initialState} is a parent state with its \ref
* state::entryState "entryState" defined, it will not be entered. The user
* must explicitly set the initial state.

10
components/bl602/bl602_wifidrv/bl60x_wifi_driver/stateMachineExample.c
View File

@ -30,19 +30,19 @@
*/
/*
/*
* Copyright (c) 2013 Andreas Misje
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@ -62,7 +62,7 @@
* "ha\n" and "hi\n". If an unrecognised character is read, a group state will
* handle this by printing a message and returning to the idle state. If the
* character '!' is encountered, a "reset" message is printed, and the group
* state's entry state will be entered (the idle state).
* state's entry state will be entered (the idle state).
*
* print 'reset'
* o +---------------------+

2
components/bl602/bl602_wifidrv/bl60x_wifi_driver/wifi.c
View File

@ -54,7 +54,7 @@
#define NET_DEBUG os_printf
#else
#define NET_DEBUG(...)
#endif
#endif
/**
****************************************************************************************
*

14
components/bl602/bl602_wifidrv/bl60x_wifi_driver/wifi_mgmr.c
View File

@ -56,7 +56,7 @@
wifi_mgmr_t wifiMgmr;
const static struct state
stateGlobal,
stateGlobal,
stateIdle,
stateConnecting,
stateConnectedIPNo, stateConnectedIPYes,
@ -128,7 +128,7 @@ char *wifi_mgmr_auth_to_str(uint8_t auth)
return "Unknown";
}
break;
default:
default:
{
return "Unknown";
}
@ -576,7 +576,7 @@ static bool stateGlobalGuard_conf_max_sta(void *ev, struct event *event )
static int auto_repeat = 0;
static void trigger_auto_denoise(void* arg)
{
//Continuously check the microwave and try to denoise
//Continuously check the microwave and try to denoise
if (auto_repeat) {
int wifi_mgmr_api_denoise_enable(void);
wifi_mgmr_api_denoise_enable();
@ -884,7 +884,7 @@ static void stateConnectedIPNoAction_ipgot(void *oldStateData, struct event *eve
USER_UNUSED(ipgot);
msg = event->data;
ipgot = (wifi_mgmr_ipgot_msg_t*)msg->data;
os_printf(DEBUG_HEADER
os_printf(DEBUG_HEADER
"IP GOT IP:%u.%u.%u.%u, "
"MASK: %u.%u.%u.%u, "
"Gateway: %u.%u.%u.%u, "
@ -951,7 +951,7 @@ static void __run_reload_tsen(void)
int16_t temp = 0;
extern void phy_tcal_callback(int16_t temperature);
if (&stateConnecting == wifiMgmr.m.currentState || &stateDisconnect == wifiMgmr.m.currentState || &stateConnectedIPYes == wifiMgmr.m.currentState ||
if (&stateConnecting == wifiMgmr.m.currentState || &stateDisconnect == wifiMgmr.m.currentState || &stateConnectedIPYes == wifiMgmr.m.currentState ||
&stateSniffer == wifiMgmr.m.currentState || &stateConnectedIPNo == wifiMgmr.m.currentState) {
bl_tsen_adc_get(&temp, 0);
phy_tcal_callback(temp);
@ -1378,7 +1378,7 @@ void wifi_mgmr_start(void)
/*TODO: use another way based on event sys?*/
hal_sys_capcode_update(255, 255);
/*periodic reload tsen */
periodic_tsen_reload(&state_tsen_reload_data, NULL);
@ -1391,7 +1391,7 @@ void wifi_mgmr_start(void)
continue;
}
ev.type = msg->ev < WIFI_MGMR_EVENT_MAXAPP_MINIFW ? EVENT_TYPE_APP :
ev.type = msg->ev < WIFI_MGMR_EVENT_MAXAPP_MINIFW ? EVENT_TYPE_APP :
(msg->ev < WIFI_MGMR_EVENT_MAXFW_MINI_GLOBAL ? EVENT_TYPE_FW : EVENT_TYPE_GLB);
stateM_handleEvent(&(wifiMgmr.m), &ev);
}

6
components/bl602/bl602_wifidrv/bl60x_wifi_driver/wifi_mgmr_cli.c
View File

@ -429,7 +429,7 @@ static void wifi_sta_ip_set_cmd(char *buf, int len, int argc, char **argv)
/* sample input
*
* cmd_ip_set 192.168.1.212 255.255.255.0 192.168.1.1 114.114.114.114 114.114.114.114
*
*
* */
uint32_t ip, mask, gw, dns1, dns2;
char addr_str[20];
@ -980,13 +980,13 @@ const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
{ "wifi_edca_dump", "dump EDCA data", wifi_edca_dump_cmd},
{ "wifi_state", "get wifi_state", cmd_wifi_state_get},
{ "wifi_update_power", "Power table test command", cmd_wifi_power_table_update},
};
};
int wifi_mgmr_cli_init(void)
{
// static command(s) do NOT need to call aos_cli_register_command(s) to register.
// However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
// XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
//return aos_cli_register_commands(cmds_user, sizeof(cmds_user)/sizeof(cmds_user[0]));
//return aos_cli_register_commands(cmds_user, sizeof(cmds_user)/sizeof(cmds_user[0]));
return 0;
}

2
components/bl602/bl602_wifidrv/bl60x_wifi_driver/wifi_mgmr_ext.c
View File

@ -689,7 +689,7 @@ int wifi_mgmr_scan_ap(char *ssid, wifi_mgmr_ap_item_t *item)
wifi_mgmr_scan_item_t *scan;
for (i = 0; i < sizeof(wifiMgmr.scan_items)/sizeof(wifiMgmr.scan_items[0]); i++) {
if (wifiMgmr.scan_items[i].is_used &&
if (wifiMgmr.scan_items[i].is_used &&
(!wifi_mgmr_scan_item_is_timeout(&wifiMgmr, &(wifiMgmr.scan_items[i]))) && 0 == strcmp(wifiMgmr.scan_items[i].ssid, ssid)) {
/*found the ssid*/
index = i;

4
components/bl602/bl602_wifidrv/bl60x_wifi_driver/wifi_mgmr_profile.c
View File

@ -48,7 +48,7 @@ int wifi_mgmr_profile_add(wifi_mgmr_t *mgmr, wifi_mgmr_profile_msg_t *profile_ms
for (i = 0; i < sizeof(mgmr->profiles)/sizeof(mgmr->profiles[0]); i++) {
if (0 == mgmr->profiles[i].isUsed) {
profile = &(mgmr->profiles[i]);
mgmr->profile_active_index = i;
os_printf("[WF][PF] Using free profile, idx is @%d\r\n", i);
break;
@ -149,7 +149,7 @@ int wifi_mgmr_profile_autoreconnect_is_enabled(wifi_mgmr_t *mgmr, int index)
{
#if 0
wifi_mgmr_profile_t *profile;
profile = __lookup_profile(mgmr, index);
if (NULL == profile) {
return -1;

2
components/bl602/freertos_riscv_ram/panic/panic_c.c
View File

@ -52,7 +52,7 @@ static void backtrace_stack(int (*print_func)(const char *fmt, ...),
uintptr_t *fp, uintptr_t *regs)
{
uintptr_t *ra;
uint32_t i = 0;
uint32_t i = 0;
while (1) {
ra = (uintptr_t *)*(unsigned long *)(fp - 1);

2
components/bl602/freertos_riscv_ram/portable/MemMang/heap_5.c
View File

@ -273,7 +273,7 @@ void *pvReturn = NULL;
void* pvPortCalloc(size_t numElements, size_t sizeOfElement)
{
void *pv = NULL;
pv=pvPortMalloc(numElements*sizeOfElement);
if(pv){
memset(pv,0,numElements*sizeOfElement);