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https://github.com/ublue-os/bazzite.git
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feat(gamescope): Add HDR patch for Kernel 6.8
This commit is contained in:
parent
a2e9928b1f
commit
f8ad9ab8f3
349
spec_files/gamescope/amd_hdr.patch
Normal file
349
spec_files/gamescope/amd_hdr.patch
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@ -0,0 +1,349 @@
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diff --git a/src/drm.cpp b/src/drm.cpp
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index c975bfd..686c9b0 100644
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--- a/src/drm.cpp
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+++ b/src/drm.cpp
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@@ -1044,15 +1044,15 @@ static bool refresh_state( drm_t *drm )
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crtc->has_vrr_enabled = crtc->props.contains( "VRR_ENABLED" );
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if (!crtc->has_vrr_enabled)
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drm_log.infof("CRTC %" PRIu32 " has no VRR_ENABLED support", crtc->id);
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- crtc->has_valve1_regamma_tf = crtc->props.contains( "VALVE1_CRTC_REGAMMA_TF" );
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- if (!crtc->has_valve1_regamma_tf)
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- drm_log.infof("CRTC %" PRIu32 " has no VALVE1_CRTC_REGAMMA_TF support", crtc->id);
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+ crtc->has_amd_regamma_tf = crtc->props.contains( "AMD_CRTC_REGAMMA_TF" );
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+ if (!crtc->has_amd_regamma_tf)
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+ drm_log.infof("CRTC %" PRIu32 " has no AMD_CRTC_REGAMMA_TF support", crtc->id);
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crtc->current.active = crtc->initial_prop_values["ACTIVE"];
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if (crtc->has_vrr_enabled)
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drm->current.vrr_enabled = crtc->initial_prop_values["VRR_ENABLED"];
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- if (crtc->has_valve1_regamma_tf)
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- drm->current.output_tf = (drm_valve1_transfer_function) crtc->initial_prop_values["VALVE1_CRTC_REGAMMA_TF"];
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+ if (crtc->has_amd_regamma_tf)
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+ drm->current.output_tf = (amdgpu_transfer_function) crtc->initial_prop_values["AMD_CRTC_REGAMMA_TF"];
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}
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for (size_t i = 0; i < drm->planes.size(); i++) {
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@@ -1060,7 +1060,7 @@ static bool refresh_state( drm_t *drm )
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if (!get_object_properties(drm, plane->id, DRM_MODE_OBJECT_PLANE, plane->props, plane->initial_prop_values)) {
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return false;
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}
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- plane->has_color_mgmt = plane->props.contains( "VALVE1_PLANE_BLEND_TF" );
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+ plane->has_color_mgmt = plane->props.contains( "AMD_PLANE_BLEND_TF" );
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}
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return true;
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@@ -1597,8 +1597,8 @@ void finish_drm(struct drm_t *drm)
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add_crtc_property(req, &drm->crtcs[i], "CTM", 0);
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if ( drm->crtcs[i].has_vrr_enabled )
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add_crtc_property(req, &drm->crtcs[i], "VRR_ENABLED", 0);
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- if ( drm->crtcs[i].has_valve1_regamma_tf )
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- add_crtc_property(req, &drm->crtcs[i], "VALVE1_CRTC_REGAMMA_TF", 0);
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+ if ( drm->crtcs[i].has_amd_regamma_tf )
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+ add_crtc_property(req, &drm->crtcs[i], "AMD_CRTC_REGAMMA_TF", 0);
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add_crtc_property(req, &drm->crtcs[i], "ACTIVE", 0);
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}
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for ( size_t i = 0; i < drm->planes.size(); i++ ) {
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@@ -1617,22 +1617,22 @@ void finish_drm(struct drm_t *drm)
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add_plane_property(req, plane, "rotation", DRM_MODE_ROTATE_0);
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if (plane->props.count("alpha") > 0)
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add_plane_property(req, plane, "alpha", 0xFFFF);
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- if (plane->props.count("VALVE1_PLANE_DEGAMMA_TF") > 0)
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- add_plane_property(req, plane, "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
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- if (plane->props.count("VALVE1_PLANE_HDR_MULT") > 0)
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- add_plane_property(req, plane, "VALVE1_PLANE_HDR_MULT", 0x100000000ULL);
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- if (plane->props.count("VALVE1_PLANE_SHAPER_TF") > 0)
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- add_plane_property(req, plane, "VALVE1_PLANE_SHAPER_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
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- if (plane->props.count("VALVE1_PLANE_SHAPER_LUT") > 0)
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- add_plane_property(req, plane, "VALVE1_PLANE_SHAPER_LUT", 0 );
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- if (plane->props.count("VALVE1_PLANE_LUT3D") > 0)
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- add_plane_property(req, plane, "VALVE1_PLANE_LUT3D", 0 );
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- if (plane->props.count("VALVE1_PLANE_BLEND_TF") > 0)
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- add_plane_property(req, plane, "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
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- if (plane->props.count("VALVE1_PLANE_BLEND_LUT") > 0)
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- add_plane_property(req, plane, "VALVE1_PLANE_BLEND_LUT", 0 );
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- if (plane->props.count("VALVE1_PLANE_CTM") > 0)
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- add_plane_property(req, plane, "VALVE1_PLANE_CTM", 0 );
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+ if (plane->props.count("AMD_PLANE_DEGAMMA_TF") > 0)
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+ add_plane_property(req, plane, "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
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+ if (plane->props.count("AMD_PLANE_HDR_MULT") > 0)
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+ add_plane_property(req, plane, "AMD_PLANE_HDR_MULT", 0x100000000ULL);
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+ if (plane->props.count("AMD_PLANE_SHAPER_TF") > 0)
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+ add_plane_property(req, plane, "AMD_PLANE_SHAPER_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
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+ if (plane->props.count("AMD_PLANE_SHAPER_LUT") > 0)
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+ add_plane_property(req, plane, "AMD_PLANE_SHAPER_LUT", 0 );
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+ if (plane->props.count("AMD_PLANE_LUT3D") > 0)
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+ add_plane_property(req, plane, "AMD_PLANE_LUT3D", 0 );
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+ if (plane->props.count("AMD_PLANE_BLEND_TF") > 0)
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+ add_plane_property(req, plane, "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
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+ if (plane->props.count("AMD_PLANE_BLEND_LUT") > 0)
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+ add_plane_property(req, plane, "AMD_PLANE_BLEND_LUT", 0 );
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+ if (plane->props.count("AMD_PLANE_CTM") > 0)
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+ add_plane_property(req, plane, "AMD_PLANE_CTM", 0 );
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}
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// We can't do a non-blocking commit here or else risk EBUSY in case the
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// previous page-flip is still in flight.
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@@ -2222,37 +2222,37 @@ struct LiftoffStateCacheEntryKasher
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std::unordered_set<LiftoffStateCacheEntry, LiftoffStateCacheEntryKasher> g_LiftoffStateCache;
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-static inline drm_valve1_transfer_function colorspace_to_plane_degamma_tf(GamescopeAppTextureColorspace colorspace)
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+static inline amdgpu_transfer_function colorspace_to_plane_degamma_tf(GamescopeAppTextureColorspace colorspace)
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{
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switch ( colorspace )
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{
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default: // Linear in this sense is SRGB. Linear = sRGB image view doing automatic sRGB -> Linear which doesn't happen on DRM side.
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case GAMESCOPE_APP_TEXTURE_COLORSPACE_SRGB:
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- return DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
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+ return AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF;
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case GAMESCOPE_APP_TEXTURE_COLORSPACE_PASSTHRU:
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case GAMESCOPE_APP_TEXTURE_COLORSPACE_SCRGB:
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// Use LINEAR TF for scRGB float format as 80 nit = 1.0 in scRGB, which matches
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// what PQ TF decodes to/encodes from.
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// AMD internal format is FP16, and generally expected for 1.0 -> 80 nit.
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// which just so happens to match scRGB.
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- return DRM_VALVE1_TRANSFER_FUNCTION_LINEAR;
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+ return AMDGPU_TRANSFER_FUNCTION_IDENTITY;
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case GAMESCOPE_APP_TEXTURE_COLORSPACE_HDR10_PQ:
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- return DRM_VALVE1_TRANSFER_FUNCTION_PQ;
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+ return AMDGPU_TRANSFER_FUNCTION_PQ_EOTF;
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}
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}
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-static inline drm_valve1_transfer_function colorspace_to_plane_shaper_tf(GamescopeAppTextureColorspace colorspace)
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+static inline amdgpu_transfer_function colorspace_to_plane_shaper_tf(GamescopeAppTextureColorspace colorspace)
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{
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switch ( colorspace )
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{
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default:
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case GAMESCOPE_APP_TEXTURE_COLORSPACE_SRGB:
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- return DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
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+ return AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF;
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case GAMESCOPE_APP_TEXTURE_COLORSPACE_SCRGB: // scRGB Linear -> PQ for shaper + 3D LUT
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case GAMESCOPE_APP_TEXTURE_COLORSPACE_HDR10_PQ:
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- return DRM_VALVE1_TRANSFER_FUNCTION_PQ;
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+ return AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF;
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case GAMESCOPE_APP_TEXTURE_COLORSPACE_PASSTHRU:
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- return DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
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+ return AMDGPU_TRANSFER_FUNCTION_DEFAULT;
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}
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}
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@@ -2403,8 +2403,8 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
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if ( drm_supports_color_mgmt( drm ) )
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{
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- drm_valve1_transfer_function degamma_tf = colorspace_to_plane_degamma_tf( entry.layerState[i].colorspace );
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- drm_valve1_transfer_function shaper_tf = colorspace_to_plane_shaper_tf( entry.layerState[i].colorspace );
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+ amdgpu_transfer_function degamma_tf = colorspace_to_plane_degamma_tf( entry.layerState[i].colorspace );
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+ amdgpu_transfer_function shaper_tf = colorspace_to_plane_shaper_tf( entry.layerState[i].colorspace );
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if ( entry.layerState[i].ycbcr )
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{
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@@ -2416,27 +2416,27 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
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//
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// Doing LINEAR/DEFAULT here introduces banding so... this is the best way.
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// (sRGB DEGAMMA does NOT work on YUV planes!)
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- degamma_tf = DRM_VALVE1_TRANSFER_FUNCTION_BT709;
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- shaper_tf = DRM_VALVE1_TRANSFER_FUNCTION_BT709;
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+ degamma_tf = AMDGPU_TRANSFER_FUNCTION_BT709_OETF;
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+ shaper_tf = AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF;
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}
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if (!g_bDisableDegamma)
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", degamma_tf );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", degamma_tf );
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else
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", 0 );
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if ( !g_bDisableShaperAnd3DLUT )
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{
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", drm->pending.shaperlut_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", shaper_tf );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", drm->pending.lut3d_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", drm->pending.shaperlut_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", shaper_tf );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", drm->pending.lut3d_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
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// Josh: See shaders/colorimetry.h colorspace_blend_tf if you have questions as to why we start doing sRGB for BLEND_TF despite potentially working in Gamma 2.2 space prior.
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}
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else
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{
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
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}
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}
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}
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@@ -2444,25 +2444,25 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
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{
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if ( drm_supports_color_mgmt( drm ) )
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{
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
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}
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}
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if ( drm_supports_color_mgmt( drm ) )
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{
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if (!g_bDisableBlendTF && !bSinglePlane)
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", drm->pending.output_tf );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", drm->pending.output_tf );
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else
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
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if (frameInfo->layers[i].ctm != nullptr)
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", frameInfo->layers[i].ctm->blob );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", frameInfo->layers[i].ctm->blob );
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else
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
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}
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}
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else
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@@ -2474,12 +2474,12 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
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if ( drm_supports_color_mgmt( drm ) )
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{
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
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- liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
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+ liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
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}
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}
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}
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@@ -2575,17 +2575,17 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
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if ( !g_bDisableRegamma && !bSinglePlane )
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{
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drm->pending.output_tf = g_bOutputHDREnabled
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- ? DRM_VALVE1_TRANSFER_FUNCTION_PQ
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- : DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
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+ ? AMDGPU_TRANSFER_FUNCTION_PQ_EOTF
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+ : AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF;
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}
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else
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{
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- drm->pending.output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
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+ drm->pending.output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
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}
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}
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else
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{
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- drm->pending.output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
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+ drm->pending.output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
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}
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uint32_t flags = DRM_MODE_ATOMIC_NONBLOCK;
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@@ -2666,9 +2666,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
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if (ret < 0)
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return ret;
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}
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- if (crtc->has_valve1_regamma_tf)
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+ if (crtc->has_amd_regamma_tf)
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{
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- int ret = add_crtc_property(drm->req, crtc, "VALVE1_CRTC_REGAMMA_TF", 0);
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+ int ret = add_crtc_property(drm->req, crtc, "AMD_CRTC_REGAMMA_TF", 0);
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if (ret < 0)
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return ret;
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}
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@@ -2719,9 +2719,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
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return ret;
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}
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- if (drm->crtc->has_valve1_regamma_tf)
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+ if (drm->crtc->has_amd_regamma_tf)
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{
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- ret = add_crtc_property(drm->req, drm->crtc, "VALVE1_CRTC_REGAMMA_TF", drm->pending.output_tf);
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+ ret = add_crtc_property(drm->req, drm->crtc, "AMD_CRTC_REGAMMA_TF", drm->pending.output_tf);
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if (ret < 0)
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return ret;
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}
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@@ -2763,9 +2763,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
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return ret;
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}
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||||
|
||||
- if ( drm->crtc->has_valve1_regamma_tf && drm->pending.output_tf != drm->current.output_tf )
|
||||
+ if ( drm->crtc->has_amd_regamma_tf && drm->pending.output_tf != drm->current.output_tf )
|
||||
{
|
||||
- int ret = add_crtc_property(drm->req, drm->crtc, "VALVE1_CRTC_REGAMMA_TF", drm->pending.output_tf );
|
||||
+ int ret = add_crtc_property(drm->req, drm->crtc, "AMD_CRTC_REGAMMA_TF", drm->pending.output_tf );
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
diff --git a/src/drm.hpp b/src/drm.hpp
|
||||
index 6810797..bc0befb 100644
|
||||
--- a/src/drm.hpp
|
||||
+++ b/src/drm.hpp
|
||||
@@ -150,7 +150,7 @@ struct crtc {
|
||||
bool has_degamma_lut;
|
||||
bool has_ctm;
|
||||
bool has_vrr_enabled;
|
||||
- bool has_valve1_regamma_tf;
|
||||
+ bool has_amd_regamma_tf;
|
||||
|
||||
struct {
|
||||
bool active;
|
||||
@@ -212,19 +212,22 @@ struct fb {
|
||||
std::atomic< uint32_t > n_refs;
|
||||
};
|
||||
|
||||
-enum drm_valve1_transfer_function {
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT,
|
||||
-
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_SRGB,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_BT709,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_PQ,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_LINEAR,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_UNITY,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_HLG,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_GAMMA22,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_GAMMA24,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_GAMMA26,
|
||||
- DRM_VALVE1_TRANSFER_FUNCTION_MAX,
|
||||
+enum amdgpu_transfer_function {
|
||||
+ AMDGPU_TRANSFER_FUNCTION_DEFAULT,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_IDENTITY,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_BT709_OETF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
|
||||
+ AMDGPU_TRANSFER_FUNCTION_COUNT
|
||||
};
|
||||
|
||||
struct drm_t {
|
||||
@@ -267,7 +270,7 @@ struct drm_t {
|
||||
uint32_t shaperlut_id[ EOTF_Count ];
|
||||
enum drm_screen_type screen_type = DRM_SCREEN_TYPE_INTERNAL;
|
||||
bool vrr_enabled = false;
|
||||
- drm_valve1_transfer_function output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
|
||||
+ amdgpu_transfer_function output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
|
||||
} current, pending;
|
||||
bool wants_vrr_enabled = false;
|
||||
|
@ -10,11 +10,18 @@ URL: https://github.com/ValveSoftware/gamescope
|
||||
|
||||
# Create stb.pc to satisfy dependency('stb')
|
||||
Source1: stb.pc
|
||||
Source2: chimeraos.patch
|
||||
Source3: crashfix.patch
|
||||
Source4: add_720p_var.patch
|
||||
Source5: touch_gestures_env.patch
|
||||
Source6: legion_go.patch
|
||||
|
||||
# https://github.com/ValveSoftware/gamescope/pull/1149
|
||||
Source2: amd_hdr.patch
|
||||
|
||||
# https://github.com/ChimeraOS/gamescope
|
||||
Source3: chimeraos.patch
|
||||
|
||||
# https://github.com/KyleGospo/gamescope
|
||||
Source4: crashfix.patch
|
||||
Source5: add_720p_var.patch
|
||||
Source6: touch_gestures_env.patch
|
||||
Source7: legion_go.patch
|
||||
|
||||
BuildRequires: meson >= 0.54.0
|
||||
BuildRequires: ninja-build
|
||||
@ -82,6 +89,7 @@ patch -Np1 < %{SOURCE3}
|
||||
patch -Np1 < %{SOURCE4}
|
||||
patch -Np1 < %{SOURCE5}
|
||||
patch -Np1 < %{SOURCE6}
|
||||
patch -Np1 < %{SOURCE7}
|
||||
|
||||
%build
|
||||
cd gamescope
|
||||
|
Loading…
x
Reference in New Issue
Block a user