diff --git a/src/drm.cpp b/src/drm.cpp
index c975bfd..686c9b0 100644
--- a/src/drm.cpp
+++ b/src/drm.cpp
@@ -1044,15 +1044,15 @@ static bool refresh_state( drm_t *drm )
 		crtc->has_vrr_enabled = crtc->props.contains( "VRR_ENABLED" );
 		if (!crtc->has_vrr_enabled)
 			drm_log.infof("CRTC %" PRIu32 " has no VRR_ENABLED support", crtc->id);
-		crtc->has_valve1_regamma_tf = crtc->props.contains( "VALVE1_CRTC_REGAMMA_TF" );
-		if (!crtc->has_valve1_regamma_tf)
-			drm_log.infof("CRTC %" PRIu32 " has no VALVE1_CRTC_REGAMMA_TF support", crtc->id);
+		crtc->has_amd_regamma_tf = crtc->props.contains( "AMD_CRTC_REGAMMA_TF" );
+		if (!crtc->has_amd_regamma_tf)
+			drm_log.infof("CRTC %" PRIu32 " has no AMD_CRTC_REGAMMA_TF support", crtc->id);
 
 		crtc->current.active = crtc->initial_prop_values["ACTIVE"];
 		if (crtc->has_vrr_enabled)
 			drm->current.vrr_enabled = crtc->initial_prop_values["VRR_ENABLED"];
-		if (crtc->has_valve1_regamma_tf)
-			drm->current.output_tf = (drm_valve1_transfer_function) crtc->initial_prop_values["VALVE1_CRTC_REGAMMA_TF"];
+		if (crtc->has_amd_regamma_tf)
+			drm->current.output_tf = (amdgpu_transfer_function) crtc->initial_prop_values["AMD_CRTC_REGAMMA_TF"];
 	}
 
 	for (size_t i = 0; i < drm->planes.size(); i++) {
@@ -1060,7 +1060,7 @@ static bool refresh_state( drm_t *drm )
 		if (!get_object_properties(drm, plane->id, DRM_MODE_OBJECT_PLANE, plane->props, plane->initial_prop_values)) {
 			return false;
 		}
-		plane->has_color_mgmt = plane->props.contains( "VALVE1_PLANE_BLEND_TF" );
+		plane->has_color_mgmt = plane->props.contains( "AMD_PLANE_BLEND_TF" );
 	}
 
 	return true;
@@ -1597,8 +1597,8 @@ void finish_drm(struct drm_t *drm)
 			add_crtc_property(req, &drm->crtcs[i], "CTM", 0);
 		if ( drm->crtcs[i].has_vrr_enabled )
 			add_crtc_property(req, &drm->crtcs[i], "VRR_ENABLED", 0);
-		if ( drm->crtcs[i].has_valve1_regamma_tf )
-			add_crtc_property(req, &drm->crtcs[i], "VALVE1_CRTC_REGAMMA_TF", 0);
+		if ( drm->crtcs[i].has_amd_regamma_tf )
+			add_crtc_property(req, &drm->crtcs[i], "AMD_CRTC_REGAMMA_TF", 0);
 		add_crtc_property(req, &drm->crtcs[i], "ACTIVE", 0);
 	}
 	for ( size_t i = 0; i < drm->planes.size(); i++ ) {
@@ -1617,22 +1617,22 @@ void finish_drm(struct drm_t *drm)
 			add_plane_property(req, plane, "rotation", DRM_MODE_ROTATE_0);
 		if (plane->props.count("alpha") > 0)
 			add_plane_property(req, plane, "alpha", 0xFFFF);
-		if (plane->props.count("VALVE1_PLANE_DEGAMMA_TF") > 0)
-			add_plane_property(req, plane, "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
-		if (plane->props.count("VALVE1_PLANE_HDR_MULT") > 0)
-			add_plane_property(req, plane, "VALVE1_PLANE_HDR_MULT", 0x100000000ULL);
-		if (plane->props.count("VALVE1_PLANE_SHAPER_TF") > 0)
-			add_plane_property(req, plane, "VALVE1_PLANE_SHAPER_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
-		if (plane->props.count("VALVE1_PLANE_SHAPER_LUT") > 0)
-			add_plane_property(req, plane, "VALVE1_PLANE_SHAPER_LUT", 0 );
-		if (plane->props.count("VALVE1_PLANE_LUT3D") > 0)
-			add_plane_property(req, plane, "VALVE1_PLANE_LUT3D", 0 );
-		if (plane->props.count("VALVE1_PLANE_BLEND_TF") > 0)
-			add_plane_property(req, plane, "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
-		if (plane->props.count("VALVE1_PLANE_BLEND_LUT") > 0)
-			add_plane_property(req, plane, "VALVE1_PLANE_BLEND_LUT", 0 );
-		if (plane->props.count("VALVE1_PLANE_CTM") > 0)
-			add_plane_property(req, plane, "VALVE1_PLANE_CTM", 0 );
+		if (plane->props.count("AMD_PLANE_DEGAMMA_TF") > 0)
+			add_plane_property(req, plane, "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
+		if (plane->props.count("AMD_PLANE_HDR_MULT") > 0)
+			add_plane_property(req, plane, "AMD_PLANE_HDR_MULT", 0x100000000ULL);
+		if (plane->props.count("AMD_PLANE_SHAPER_TF") > 0)
+			add_plane_property(req, plane, "AMD_PLANE_SHAPER_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
+		if (plane->props.count("AMD_PLANE_SHAPER_LUT") > 0)
+			add_plane_property(req, plane, "AMD_PLANE_SHAPER_LUT", 0 );
+		if (plane->props.count("AMD_PLANE_LUT3D") > 0)
+			add_plane_property(req, plane, "AMD_PLANE_LUT3D", 0 );
+		if (plane->props.count("AMD_PLANE_BLEND_TF") > 0)
+			add_plane_property(req, plane, "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
+		if (plane->props.count("AMD_PLANE_BLEND_LUT") > 0)
+			add_plane_property(req, plane, "AMD_PLANE_BLEND_LUT", 0 );
+		if (plane->props.count("AMD_PLANE_CTM") > 0)
+			add_plane_property(req, plane, "AMD_PLANE_CTM", 0 );
 	}
 	// We can't do a non-blocking commit here or else risk EBUSY in case the
 	// previous page-flip is still in flight.
@@ -2222,37 +2222,37 @@ struct LiftoffStateCacheEntryKasher
 
 std::unordered_set<LiftoffStateCacheEntry, LiftoffStateCacheEntryKasher> g_LiftoffStateCache;
 
-static inline drm_valve1_transfer_function colorspace_to_plane_degamma_tf(GamescopeAppTextureColorspace colorspace)
+static inline amdgpu_transfer_function colorspace_to_plane_degamma_tf(GamescopeAppTextureColorspace colorspace)
 {
 	switch ( colorspace )
 	{
 		default: // Linear in this sense is SRGB. Linear = sRGB image view doing automatic sRGB -> Linear which doesn't happen on DRM side.
 		case GAMESCOPE_APP_TEXTURE_COLORSPACE_SRGB:
-			return DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
+			return AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF;
 		case GAMESCOPE_APP_TEXTURE_COLORSPACE_PASSTHRU:
 		case GAMESCOPE_APP_TEXTURE_COLORSPACE_SCRGB:
 			// Use LINEAR TF for scRGB float format as 80 nit = 1.0 in scRGB, which matches
 			// what PQ TF decodes to/encodes from.
 			// AMD internal format is FP16, and generally expected for 1.0 -> 80 nit.
 			// which just so happens to match scRGB.
-			return DRM_VALVE1_TRANSFER_FUNCTION_LINEAR;
+			return AMDGPU_TRANSFER_FUNCTION_IDENTITY;
 		case GAMESCOPE_APP_TEXTURE_COLORSPACE_HDR10_PQ:
-			return DRM_VALVE1_TRANSFER_FUNCTION_PQ;
+			return AMDGPU_TRANSFER_FUNCTION_PQ_EOTF;
 	}
 }
 
-static inline drm_valve1_transfer_function colorspace_to_plane_shaper_tf(GamescopeAppTextureColorspace colorspace)
+static inline amdgpu_transfer_function colorspace_to_plane_shaper_tf(GamescopeAppTextureColorspace colorspace)
 {
 	switch ( colorspace )
 	{
 		default:
 		case GAMESCOPE_APP_TEXTURE_COLORSPACE_SRGB:
-			return DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
+			return AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF;
 		case GAMESCOPE_APP_TEXTURE_COLORSPACE_SCRGB: // scRGB Linear -> PQ for shaper + 3D LUT
 		case GAMESCOPE_APP_TEXTURE_COLORSPACE_HDR10_PQ:
-			return DRM_VALVE1_TRANSFER_FUNCTION_PQ;
+			return AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF;
 		case GAMESCOPE_APP_TEXTURE_COLORSPACE_PASSTHRU:
-			return DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
+			return AMDGPU_TRANSFER_FUNCTION_DEFAULT;
 	}
 }
 
@@ -2403,8 +2403,8 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
 
 				if ( drm_supports_color_mgmt( drm ) )
 				{
-					drm_valve1_transfer_function degamma_tf = colorspace_to_plane_degamma_tf( entry.layerState[i].colorspace );
-					drm_valve1_transfer_function shaper_tf = colorspace_to_plane_shaper_tf( entry.layerState[i].colorspace );
+					amdgpu_transfer_function degamma_tf = colorspace_to_plane_degamma_tf( entry.layerState[i].colorspace );
+					amdgpu_transfer_function shaper_tf = colorspace_to_plane_shaper_tf( entry.layerState[i].colorspace );
 
 					if ( entry.layerState[i].ycbcr )
 					{
@@ -2416,27 +2416,27 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
 						//
 						// Doing LINEAR/DEFAULT here introduces banding so... this is the best way.
 						// (sRGB DEGAMMA does NOT work on YUV planes!)
-						degamma_tf = DRM_VALVE1_TRANSFER_FUNCTION_BT709;
-						shaper_tf = DRM_VALVE1_TRANSFER_FUNCTION_BT709;
+						degamma_tf = AMDGPU_TRANSFER_FUNCTION_BT709_OETF;
+						shaper_tf = AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF;
 					}
 
 					if (!g_bDisableDegamma)
-						liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", degamma_tf );
+						liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", degamma_tf );
 					else
-						liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", 0 );
+						liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", 0 );
 
 					if ( !g_bDisableShaperAnd3DLUT )
 					{
-						liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", drm->pending.shaperlut_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
-						liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", shaper_tf );
-						liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", drm->pending.lut3d_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
+						liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", drm->pending.shaperlut_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
+						liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", shaper_tf );
+						liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", drm->pending.lut3d_id[ ColorSpaceToEOTFIndex( entry.layerState[i].colorspace ) ] );
 						// Josh: See shaders/colorimetry.h colorspace_blend_tf if you have questions as to why we start doing sRGB for BLEND_TF despite potentially working in Gamma 2.2 space prior.
 					}
 					else
 					{
-						liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
-						liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
-						liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
+						liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
+						liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
+						liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
 					}
 				}
 			}
@@ -2444,25 +2444,25 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
 			{
 				if ( drm_supports_color_mgmt( drm ) )
 				{
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
 				}
 			}
 
 			if ( drm_supports_color_mgmt( drm ) )
 			{
 				if (!g_bDisableBlendTF && !bSinglePlane)
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", drm->pending.output_tf );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", drm->pending.output_tf );
 				else
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
 
 				if (frameInfo->layers[i].ctm != nullptr)
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", frameInfo->layers[i].ctm->blob );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", frameInfo->layers[i].ctm->blob );
 				else
-					liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
+					liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
 			}
 		}
 		else
@@ -2474,12 +2474,12 @@ drm_prepare_liftoff( struct drm_t *drm, const struct FrameInfo_t *frameInfo, boo
 
 			if ( drm_supports_color_mgmt( drm ) )
 			{
-				liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_DEGAMMA_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
-				liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_LUT", 0 );
-				liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_SHAPER_TF", 0 );
-				liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_LUT3D", 0 );
-				liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_BLEND_TF", DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT );
-				liftoff_layer_set_property( drm->lo_layers[ i ], "VALVE1_PLANE_CTM", 0 );
+				liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_DEGAMMA_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
+				liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_LUT", 0 );
+				liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_SHAPER_TF", 0 );
+				liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_LUT3D", 0 );
+				liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_BLEND_TF", AMDGPU_TRANSFER_FUNCTION_DEFAULT );
+				liftoff_layer_set_property( drm->lo_layers[ i ], "AMD_PLANE_CTM", 0 );
 			}
 		}
 	}
@@ -2575,17 +2575,17 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
 		if ( !g_bDisableRegamma && !bSinglePlane )
 		{
 			drm->pending.output_tf = g_bOutputHDREnabled
-				? DRM_VALVE1_TRANSFER_FUNCTION_PQ
-				: DRM_VALVE1_TRANSFER_FUNCTION_SRGB;
+				? AMDGPU_TRANSFER_FUNCTION_PQ_EOTF
+				: AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF;
 		}
 		else
 		{
-			drm->pending.output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
+			drm->pending.output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
 		}
 	}
 	else
 	{
-		drm->pending.output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
+		drm->pending.output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
 	}
 
 	uint32_t flags = DRM_MODE_ATOMIC_NONBLOCK;
@@ -2666,9 +2666,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
 				if (ret < 0)
 					return ret;
 			}
-			if (crtc->has_valve1_regamma_tf)
+			if (crtc->has_amd_regamma_tf)
 			{
-				int ret = add_crtc_property(drm->req, crtc, "VALVE1_CRTC_REGAMMA_TF", 0);
+				int ret = add_crtc_property(drm->req, crtc, "AMD_CRTC_REGAMMA_TF", 0);
 				if (ret < 0)
 					return ret;
 			}
@@ -2719,9 +2719,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
 					return ret;
 			}
 
-			if (drm->crtc->has_valve1_regamma_tf)
+			if (drm->crtc->has_amd_regamma_tf)
 			{
-				ret = add_crtc_property(drm->req, drm->crtc, "VALVE1_CRTC_REGAMMA_TF", drm->pending.output_tf);
+				ret = add_crtc_property(drm->req, drm->crtc, "AMD_CRTC_REGAMMA_TF", drm->pending.output_tf);
 				if (ret < 0)
 					return ret;
 			}
@@ -2763,9 +2763,9 @@ int drm_prepare( struct drm_t *drm, bool async, const struct FrameInfo_t *frameI
 					return ret;
 			}
 
-			if ( drm->crtc->has_valve1_regamma_tf && drm->pending.output_tf != drm->current.output_tf )
+			if ( drm->crtc->has_amd_regamma_tf && drm->pending.output_tf != drm->current.output_tf )
 			{
-				int ret = add_crtc_property(drm->req, drm->crtc, "VALVE1_CRTC_REGAMMA_TF", drm->pending.output_tf );
+				int ret = add_crtc_property(drm->req, drm->crtc, "AMD_CRTC_REGAMMA_TF", drm->pending.output_tf );
 				if (ret < 0)
 					return ret;
 			}
diff --git a/src/drm.hpp b/src/drm.hpp
index 6810797..bc0befb 100644
--- a/src/drm.hpp
+++ b/src/drm.hpp
@@ -150,7 +150,7 @@ struct crtc {
 	bool has_degamma_lut;
 	bool has_ctm;
 	bool has_vrr_enabled;
-	bool has_valve1_regamma_tf;
+	bool has_amd_regamma_tf;
 
 	struct {
 		bool active;
@@ -212,19 +212,22 @@ struct fb {
 	std::atomic< uint32_t > n_refs;
 };
 
-enum drm_valve1_transfer_function {
-	DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT,
-
-	DRM_VALVE1_TRANSFER_FUNCTION_SRGB,
-	DRM_VALVE1_TRANSFER_FUNCTION_BT709,
-	DRM_VALVE1_TRANSFER_FUNCTION_PQ,
-	DRM_VALVE1_TRANSFER_FUNCTION_LINEAR,
-	DRM_VALVE1_TRANSFER_FUNCTION_UNITY,
-	DRM_VALVE1_TRANSFER_FUNCTION_HLG,
-	DRM_VALVE1_TRANSFER_FUNCTION_GAMMA22,
-	DRM_VALVE1_TRANSFER_FUNCTION_GAMMA24,
-	DRM_VALVE1_TRANSFER_FUNCTION_GAMMA26,
-	DRM_VALVE1_TRANSFER_FUNCTION_MAX,
+enum amdgpu_transfer_function {
+	AMDGPU_TRANSFER_FUNCTION_DEFAULT,
+	AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,
+	AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_IDENTITY,
+	AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_BT709_OETF,
+	AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
+	AMDGPU_TRANSFER_FUNCTION_COUNT
 };
 
 struct drm_t {
@@ -267,7 +270,7 @@ struct drm_t {
 		uint32_t shaperlut_id[ EOTF_Count ];
 		enum drm_screen_type screen_type = DRM_SCREEN_TYPE_INTERNAL;
 		bool vrr_enabled = false;
-		drm_valve1_transfer_function output_tf = DRM_VALVE1_TRANSFER_FUNCTION_DEFAULT;
+		amdgpu_transfer_function output_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;
 	} current, pending;
 	bool wants_vrr_enabled = false;
 
