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https://github.com/libretro/RetroArch
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381 lines
6.5 KiB
ArmAsm
381 lines
6.5 KiB
ArmAsm
#include <asm.h>
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.globl __realmode
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__realmode:
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clrlwi r3,r3,2
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mtsrr0 r3
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mfmsr r3
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rlwinm r3,r3,0,28,25
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mtsrr1 r3
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rfi
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// complete init sequence taken from bootmii's ppc skeleton. thanks to segher
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// after a talk with dhewg we came to that point that it's good to wipe+setup BATS correctly
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.globl __configBATS
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__configBATS:
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// HID0 = 00110c64:
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// bus checkstops off, sleep modes off,
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// caches off, caches invalidate,
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// store gathering off, enable data cache
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// flush assist, enable branch target cache,
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// enable branch history table
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lis r3,0x0011
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ori r3,r3,0x0c64
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mtspr HID0,r3
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isync
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#if defined(HW_RVL)
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lis r3,0x8200 //bits set: H4A(HID4 access), SBE(2nd BAT enabled)
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mtspr HID4,r3
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isync
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#endif
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// clear all BATs
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li r0,0
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mtspr IBAT0U,r0; mtspr IBAT1U,r0; mtspr IBAT2U,r0; mtspr IBAT3U,r0 // IBAT0...3
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mtspr DBAT0U,r0; mtspr DBAT1U,r0; mtspr DBAT2U,r0; mtspr DBAT3U,r0 // DBAT0...3
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#if defined(HW_RVL)
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mtspr IBAT4U,r0; mtspr IBAT5U,r0; mtspr IBAT6U,r0; mtspr IBAT7U,r0 // IBAT4...7
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mtspr DBAT4U,r0; mtspr DBAT5U,r0; mtspr DBAT6U,r0; mtspr DBAT7U,r0 // DBAT4...7
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#endif
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isync
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// clear all SRs
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lis r0,0x8000
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mtsr 0,r0; mtsr 1,r0; mtsr 2,r0; mtsr 3,r0; mtsr 4,r0; mtsr 5,r0; mtsr 6,r0
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mtsr 7,r0; mtsr 8,r0; mtsr 9,r0; mtsr 10,r0; mtsr 11,r0; mtsr 12,r0; mtsr 13,r0
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mtsr 14,r0; mtsr 15,r0
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isync
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// set [DI]BAT0 for 256MB@80000000,
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// real 00000000, WIMG=0000, R/W
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li r3,2
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lis r4,0x8000
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ori r4,r4,0x1fff
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mtspr IBAT0L,r3
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mtspr IBAT0U,r4
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mtspr DBAT0L,r3
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mtspr DBAT0U,r4
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isync
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#if defined(HW_RVL)
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// set [DI]BAT4 for 256MB@90000000,
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// real 10000000, WIMG=0000, R/W
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addis r3,r3,0x1000
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addis r4,r4,0x1000
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mtspr IBAT4L,r3
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mtspr IBAT4U,r4
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mtspr DBAT4L,r3
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mtspr DBAT4U,r4
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isync
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#endif
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// set DBAT1 for 256MB@c0000000,
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// real 00000000, WIMG=0101, R/W
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li r3,0x2a
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lis r4,0xc000
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ori r4,r4,0x1fff
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mtspr DBAT1L,r3
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mtspr DBAT1U,r4
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isync
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#if defined(HW_RVL)
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// set DBAT5 for 256MB@d0000000,
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// real 10000000, WIMG=0101, R/W
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addis r3,r3,0x1000
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addis r4,r4,0x1000
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mtspr DBAT5L,r3
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mtspr DBAT5U,r4
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isync
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#endif
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mfmsr r3
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ori r3,r3,MSR_DR|MSR_IR
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mtsrr1 r3
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mflr r3
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oris r3,r3,0x8000
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mtsrr0 r3
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rfi
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.globl __InitFPRS
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__InitFPRS:
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# Enable the Floating Point Registers
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mfmsr r3
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ori r3,r3,MSR_FP
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mtmsr r3
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mfspr r3,920
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extrwi. r3,r3,1,2
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beq 1f
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# Clear all of the PS FPR's to 0
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lis r3,zeroPS@ha
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addi r3,r3,zeroPS@l
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psq_l fr0,0(r3),0,0
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ps_mr fr1,fr0
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ps_mr fr2,fr0
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ps_mr fr3,fr0
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ps_mr fr4,fr0
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ps_mr fr5,fr0
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ps_mr fr6,fr0
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ps_mr fr7,fr0
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ps_mr fr8,fr0
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ps_mr fr9,fr0
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ps_mr fr10,fr0
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ps_mr fr11,fr0
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ps_mr fr12,fr0
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ps_mr fr13,fr0
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ps_mr fr14,fr0
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ps_mr fr15,fr0
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ps_mr fr16,fr0
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ps_mr fr17,fr0
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ps_mr fr18,fr0
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ps_mr fr19,fr0
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ps_mr fr20,fr0
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ps_mr fr21,fr0
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ps_mr fr22,fr0
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ps_mr fr23,fr0
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ps_mr fr24,fr0
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ps_mr fr25,fr0
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ps_mr fr26,fr0
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ps_mr fr27,fr0
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ps_mr fr28,fr0
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ps_mr fr29,fr0
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ps_mr fr30,fr0
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ps_mr fr31,fr0
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# Clear all of the FPR's to 0
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1: lis r3,zeroF@ha
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lfd fr0,zeroF@l(r3)
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fmr fr1,fr0
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fmr fr2,fr0
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fmr fr3,fr0
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fmr fr4,fr0
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fmr fr5,fr0
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fmr fr6,fr0
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fmr fr7,fr0
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fmr fr8,fr0
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fmr fr9,fr0
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fmr fr10,fr0
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fmr fr11,fr0
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fmr fr12,fr0
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fmr fr13,fr0
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fmr fr14,fr0
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fmr fr15,fr0
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fmr fr16,fr0
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fmr fr17,fr0
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fmr fr18,fr0
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fmr fr19,fr0
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fmr fr20,fr0
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fmr fr21,fr0
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fmr fr22,fr0
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fmr fr23,fr0
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fmr fr24,fr0
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fmr fr25,fr0
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fmr fr26,fr0
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fmr fr27,fr0
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fmr fr28,fr0
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fmr fr29,fr0
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fmr fr30,fr0
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fmr fr31,fr0
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mtfsf 255,fr0
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# Return
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blr
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.extern ICFlashInvalidate
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.globl __InitPS
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__InitPS:
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mflr r0
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stw r0,4(sp)
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stwu sp,-8(sp)
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mfspr r3,HID2
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oris r3,r3,0xA000
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mtspr HID2,r3
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isync
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bl ICFlashInvalidate
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sync
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li r3,0
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mtspr GQR0,r3
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mtspr GQR1,r3
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mtspr GQR2,r3
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mtspr GQR3,r3
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mtspr GQR4,r3
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mtspr GQR5,r3
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mtspr GQR6,r3
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mtspr GQR7,r3
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isync
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lwz r0,12(sp)
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addi sp,sp,8
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mtlr r0
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blr
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.extern ICEnable
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.extern DCEnable
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.extern L2Init
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.extern L2Enable
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.globl __InitCache
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__InitCache:
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mflr r0
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stw r0, 4(sp)
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stwu sp, -16(sp)
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stw r31, 12(sp)
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mfspr r3,HID0
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rlwinm. r0,r3, 0, 16, 16 // Check if the Instruction Cache has been enabled or not.
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bne ICEnabled
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bl ICEnable
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ICEnabled:
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mfspr r3, HID0
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rlwinm. r0, r3, 0, 17, 17 // Check if the Data Cache has been enabled or not.
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bne DCEnabled
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bl DCEnable
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DCEnabled:
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mfspr r3, L2CR
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clrrwi. r0, r3, 31 // Check if the Locked Cache has been enabled or not.
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bne L2Enabled
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bl L2Init
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bl L2Enable
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L2Enabled:
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# Restore the non-volatile registers to their previous values and return.
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lwz r0, 20(sp)
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lwz r31, 12(sp)
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addi sp, sp, 16
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mtlr r0
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blr
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.globl __InitSystem
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__InitSystem:
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mflr r0
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stw r0, 4(sp)
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stwu sp, -24(sp)
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stmw r29, 12(sp)
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# Disable interrupts!
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mfmsr r3
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rlwinm r4,r3,0,17,15
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rlwinm r4,r4,0,26,24
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mtmsr r4
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# Clear various SPR's
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li r3,0
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mtspr 952, r3
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mtspr 956, r3
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mtspr 953, r3
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mtspr 954, r3
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mtspr 957, r3
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mtspr 958, r3
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isync
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#if defined(HW_RVL)
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mfspr r3,HID4
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oris r3,r3,0x0190 //set additional bits in HID4: SR0(store 0), LPE(PS LE exception), L2CFI(L2 castout prior to L2 inv. flash)
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mtspr HID4,r3
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isync
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#endif
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# Disable Speculative Bus Accesses to non-guarded space from both caches.
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mfspr r3, HID0
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ori r3, r3, 0x0200
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mtspr HID0, r3
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isync
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# Set the Non-IEEE mode in the FPSCR
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mtfsb1 29
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# Disable Write Gather Pipe
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mfspr r3,HID2 # (HID2)
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rlwinm r3, r3, 0, 2, 0
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mtspr HID2,r3 # (HID2)
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isync
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# Restore the non-volatile registers to their previous values and return.
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lwz r0, 28(sp)
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lmw r29,12(sp)
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addi sp, sp, 24
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mtlr r0
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blr
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.globl __flush_cache
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__flush_cache:
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lis r5,0xffff
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ori r5,r5,0xfff1
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and r5,r5,r3
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subf r3,r5,r3
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add r4,r4,r3
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1: dcbst r0,r5
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sync
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icbi r0,r5
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addic r5,r5,8
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subic. r4,r4,8
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bge 1b
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sync
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blr
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.globl __reset
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__reset:
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b 1f
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9: mfspr r8,HID0
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ori r8,r8,0x0008
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mtspr HID0,r8
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isync
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sync
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nop
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b 2f
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1: b 3f
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2: mftb r5
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4: mftb r6
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subf r7,r5,r6
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cmplwi r7,0x1124
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blt 4b
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nop
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b 5f
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3: b 6f
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5: lis r8,0xCC00
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ori r8,r8,0x3000
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li r4,3
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stw r4,36(r8)
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stw r3,36(r8)
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nop
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b 7f
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6: b 8f
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7: nop
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b 7b
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8: b 9b
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.globl __InitBATS
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__InitBATS:
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mflr r31
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oris r31,r31,0x8000
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lis r3,__configBATS@h
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ori r3,r3,__configBATS@l
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bl __realmode
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mtlr r31
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blr
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.globl SYS_SwitchFiber
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SYS_SwitchFiber:
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mflr r0
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mr r9,sp
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stwu r9,-8(r8)
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mr sp,r8
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stw r0,4(r9)
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mtlr r7
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blrl
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lwz r5,0(sp)
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lwz r0,4(r5)
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mtlr r0
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mr sp,r5
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blr
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.section .data
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.balign 4
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zeroF:
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.double 0.0
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zeroPS:
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.float 0.0,0.0
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