mirror of
https://github.com/libretro/RetroArch
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170 lines
2.8 KiB
ArmAsm
170 lines
2.8 KiB
ArmAsm
#include <asm.h>
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#define EXCEPTION_PROLOG \
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mfspr r0,912; \
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stw r0,GQR0_OFFSET(sp); \
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mfspr r0,913; \
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stw r0,GQR1_OFFSET(sp); \
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mfspr r0,914; \
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stw r0,GQR2_OFFSET(sp); \
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mfspr r0,915; \
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stw r0,GQR3_OFFSET(sp); \
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mfspr r0,916; \
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stw r0,GQR4_OFFSET(sp); \
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mfspr r0,917; \
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stw r0,GQR5_OFFSET(sp); \
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mfspr r0,918; \
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stw r0,GQR6_OFFSET(sp); \
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mfspr r0,919; \
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stw r0,GQR7_OFFSET(sp); \
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stmw r6,GPR6_OFFSET(sp)
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#define EXCEPTION_EPILOG \
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lwz r4,GQR0_OFFSET(sp); \
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mtspr 912,r4; \
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lwz r4,GQR1_OFFSET(sp); \
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mtspr 913,r4; \
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lwz r4,GQR2_OFFSET(sp); \
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mtspr 914,r4; \
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lwz r4,GQR3_OFFSET(sp); \
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mtspr 915,r4; \
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lwz r4,GQR4_OFFSET(sp); \
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mtspr 916,r4; \
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lwz r4,GQR5_OFFSET(sp); \
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mtspr 917,r4; \
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lwz r4,GQR6_OFFSET(sp); \
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mtspr 918,r4; \
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lwz r4,GQR7_OFFSET(sp); \
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mtspr 919,r4; \
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lmw r5,GPR5_OFFSET(sp)
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.extern c_debug_handler
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.extern _cpu_context_save_fp
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.globl dbg_exceptionhandler
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dbg_exceptionhandler:
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stwu sp,-EXCEPTION_FRAME_END(sp) //now we're able to adjust the stackpointer with it's cached address
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EXCEPTION_PROLOG
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mfmsr r4
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ori r4,r4,MSR_FP
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mtmsr r4
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isync
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addi r14,sp,0
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lis r15,__debug_nestlevel@ha
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lwz r6,__debug_nestlevel@l(r15)
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cmpwi r6,0
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bne nested
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lis sp,__debugstack@h
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ori sp,sp,__debugstack@l
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lis r0,0
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stwu r0,-16(sp)
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nested:
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addi r6,r6,1
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stw r6,__debug_nestlevel@l(r15)
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addi r3,r14,0x08
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bl _cpu_context_save_fp
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bl c_debug_handler
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lwz r6,__debug_nestlevel@l(r15)
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addi r6,r6,-1
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stw r6,__debug_nestlevel@l(r15)
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addi sp,r14,0
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exit:
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lwz r4,CR_OFFSET(sp)
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mtcr r4
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lwz r4,LR_OFFSET(sp)
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mtlr r4
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lwz r4,CTR_OFFSET(sp)
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mtctr r4
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lwz r4,XER_OFFSET(sp)
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mtxer r4
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EXCEPTION_EPILOG
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mfmsr r4
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rlwinm r4,r4,0,19,17
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mtmsr r4
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isync
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lwz toc,GPR2_OFFSET(sp)
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lwz r0,GPR0_OFFSET(sp)
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lwz r4,SRR0_OFFSET(sp)
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mtsrr0 r4
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lwz r4,SRR1_OFFSET(sp)
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mtsrr1 r4
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lwz r4,GPR4_OFFSET(sp)
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lwz r3,GPR3_OFFSET(sp)
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addi sp,sp,EXCEPTION_FRAME_END
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rfi
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.globl __set_iabr
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__set_iabr:
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mfmsr r4
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rlwinm r5,r4,0,18,16
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mtmsr r5
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clrrwi r3,r3,2
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mtspr 1010,r3
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isync
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sync
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mtmsr r4
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blr
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.globl __enable_iabr
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__enable_iabr:
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mfmsr r4
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rlwinm r5,r4,0,18,16
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mtmsr r5
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mfspr r3,1010
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ori r3,r3,0x0003
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mtspr 1010,r3
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isync
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sync
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mtmsr r4
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blr
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.globl __disable_iabr
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__disable_iabr:
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mfmsr r4
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rlwinm r5,r4,0,18,16
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mtmsr r5
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mfspr r3,1010
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clrrwi r3,r3,2
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mtspr 1010,r3
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isync
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sync
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mtmsr r4
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blr
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.globl __clr_iabr
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__clr_iabr:
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mfmsr r4
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rlwinm r5,r4,0,18,16
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mtmsr r5
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mtspr 1010,0
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isync
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sync
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mtmsr r4
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blr
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.section .bss
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.balign 4
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__debug_nestlevel:
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.long 0
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.balign 8
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.globl __debugstack_end,__debugstack
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__debugstack_end:
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.space 0x4000
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__debugstack:
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