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Add SSSE3 detection as well.
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@ -222,14 +222,18 @@ void rarch_get_cpu_features(struct rarch_cpu_features *cpu)
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if (flags[2] & (1 << 0))
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cpu->simd |= RARCH_SIMD_SSE3;
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if (flags[2] & (1 << 9))
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cpu->simd |= RARCH_SIMD_SSSE3;
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const int avx_flags = (1 << 27) | (1 << 28);
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if ((flags[2] & avx_flags) == avx_flags)
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cpu->simd |= RARCH_SIMD_AVX;
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RARCH_LOG("[CPUID]: SSE: %u\n", !!(cpu->simd & RARCH_SIMD_SSE));
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RARCH_LOG("[CPUID]: SSE2: %u\n", !!(cpu->simd & RARCH_SIMD_SSE2));
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RARCH_LOG("[CPUID]: SSE3: %u\n", !!(cpu->simd & RARCH_SIMD_SSE3));
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RARCH_LOG("[CPUID]: AVX: %u\n", !!(cpu->simd & RARCH_SIMD_AVX));
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RARCH_LOG("[CPUID]: SSE: %u\n", !!(cpu->simd & RARCH_SIMD_SSE));
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RARCH_LOG("[CPUID]: SSE2: %u\n", !!(cpu->simd & RARCH_SIMD_SSE2));
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RARCH_LOG("[CPUID]: SSE3: %u\n", !!(cpu->simd & RARCH_SIMD_SSE3));
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RARCH_LOG("[CPUID]: SSSE3: %u\n", !!(cpu->simd & RARCH_SIMD_SSSE3));
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RARCH_LOG("[CPUID]: AVX: %u\n", !!(cpu->simd & RARCH_SIMD_AVX));
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#elif defined(ANDROID) && defined(ANDROID_ARM)
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uint64_t cpu_flags = android_getCpuFeatures();
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@ -58,6 +58,7 @@ struct rarch_cpu_features
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#define RARCH_SIMD_AVX (1 << 4)
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#define RARCH_SIMD_NEON (1 << 5)
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#define RARCH_SIMD_SSE3 (1 << 6)
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#define RARCH_SIMD_SSSE3 (1 << 7)
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void rarch_get_cpu_features(struct rarch_cpu_features *cpu);
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