mirror of
https://github.com/libretro/RetroArch
synced 2025-02-01 20:54:10 +00:00
252 lines
6.2 KiB
C
252 lines
6.2 KiB
C
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#ifndef __PROCESSOR_H__
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#define __PROCESSOR_H__
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#include <gctypes.h>
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#include "asm.h"
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#define __stringify(rn) #rn
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#define ATTRIBUTE_ALIGN(v) __attribute__((aligned(v)))
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// courtesy of Marcan
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#define STACK_ALIGN(type, name, cnt, alignment) u8 _al__##name[((sizeof(type)*(cnt)) + (alignment) + (((sizeof(type)*(cnt))%(alignment)) > 0 ? ((alignment) - ((sizeof(type)*(cnt))%(alignment))) : 0))]; \
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type *name = (type*)(((u32)(_al__##name)) + ((alignment) - (((u32)(_al__##name))&((alignment)-1))))
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#define _sync() asm volatile("sync")
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#define _nop() asm volatile("nop")
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#define ppcsync() asm volatile("sc")
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#define ppchalt() ({ \
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asm volatile("sync"); \
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while(1) { \
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asm volatile("nop"); \
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asm volatile("li 3,0"); \
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asm volatile("nop"); \
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} \
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})
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#define mfpvr() ({register u32 _rval; \
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asm volatile("mfpvr %0" : "=r"(_rval)); _rval;})
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#define mfdcr(_rn) ({register u32 _rval; \
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asm volatile("mfdcr %0," __stringify(_rn) \
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: "=r" (_rval)); _rval;})
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#define mtdcr(rn, val) asm volatile("mtdcr " __stringify(rn) ",%0" : : "r" (val))
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#define mfmsr() ({register u32 _rval; \
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asm volatile("mfmsr %0" : "=r" (_rval)); _rval;})
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#define mtmsr(val) asm volatile("mtmsr %0" : : "r" (val))
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#define mfdec() ({register u32 _rval; \
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asm volatile("mfdec %0" : "=r" (_rval)); _rval;})
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#define mtdec(_val) asm volatile("mtdec %0" : : "r" (_val))
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#define mfspr(_rn) \
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({ register u32 _rval = 0; \
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asm volatile("mfspr %0," __stringify(_rn) \
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: "=r" (_rval));\
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_rval; \
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})
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#define mtspr(_rn, _val) asm volatile("mtspr " __stringify(_rn) ",%0" : : "r" (_val))
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#define mfwpar() mfspr(WPAR)
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#define mtwpar(_val) mtspr(WPAR,_val)
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#define mfmmcr0() mfspr(MMCR0)
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#define mtmmcr0(_val) mtspr(MMCR0,_val)
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#define mfmmcr1() mfspr(MMCR1)
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#define mtmmcr1(_val) mtspr(MMCR1,_val)
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#define mfpmc1() mfspr(PMC1)
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#define mtpmc1(_val) mtspr(PMC1,_val)
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#define mfpmc2() mfspr(PMC2)
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#define mtpmc2(_val) mtspr(PMC2,_val)
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#define mfpmc3() mfspr(PMC3)
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#define mtpmc3(_val) mtspr(PMC3,_val)
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#define mfpmc4() mfspr(PMC4)
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#define mtpmc4(_val) mtspr(PMC4,_val)
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#define mfhid0() mfspr(HID0)
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#define mthid0(_val) mtspr(HID0,_val)
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#define mfhid1() mfspr(HID1)
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#define mthid1(_val) mtspr(HID1,_val)
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#define mfhid2() mfspr(HID2)
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#define mthid2(_val) mtspr(HID2,_val)
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#define mfhid4() mfspr(HID4)
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#define mthid4(_val) mtspr(HID4,_val)
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#define __lhbrx(base,index) \
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({ register u16 res; \
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__asm__ volatile ("lhbrx %0,%1,%2" : "=r"(res) : "b%"(index), "r"(base) : "memory"); \
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res; })
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#define __lwbrx(base,index) \
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({ register u32 res; \
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__asm__ volatile ("lwbrx %0,%1,%2" : "=r"(res) : "b%"(index), "r"(base) : "memory"); \
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res; })
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#define __sthbrx(base,index,value) \
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__asm__ volatile ("sthbrx %0,%1,%2" : : "r"(value), "b%"(index), "r"(base) : "memory")
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#define __stwbrx(base,index,value) \
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__asm__ volatile ("stwbrx %0,%1,%2" : : "r"(value), "b%"(index), "r"(base) : "memory")
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#define cntlzw(_val) ({register u32 _rval; \
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asm volatile("cntlzw %0, %1" : "=r"((_rval)) : "r"((_val))); _rval;})
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#define _CPU_MSR_GET( _msr_value ) \
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do { \
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_msr_value = 0; \
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asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
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} while (0)
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#define _CPU_MSR_SET( _msr_value ) \
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{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
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#define _CPU_ISR_Enable() \
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{ register u32 _val = 0; \
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__asm__ __volatile__ ( \
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"mfmsr %0\n" \
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"ori %0,%0,0x8000\n" \
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"mtmsr %0" \
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: "=&r" ((_val)) : "0" ((_val)) \
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); \
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}
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#define _CPU_ISR_Disable( _isr_cookie ) \
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{ register u32 _disable_mask = 0; \
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_isr_cookie = 0; \
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__asm__ __volatile__ ( \
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"mfmsr %0\n" \
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"rlwinm %1,%0,0,17,15\n" \
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"mtmsr %1\n" \
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"extrwi %0,%0,1,16" \
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: "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) \
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: "0" ((_isr_cookie)), "1" ((_disable_mask)) \
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); \
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}
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#define _CPU_ISR_Restore( _isr_cookie ) \
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{ register u32 _enable_mask = 0; \
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__asm__ __volatile__ ( \
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" cmpwi %0,0\n" \
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" beq 1f\n" \
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" mfmsr %1\n" \
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" ori %1,%1,0x8000\n" \
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" mtmsr %1\n" \
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"1:" \
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: "=r"((_isr_cookie)),"=&r" ((_enable_mask)) \
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: "0"((_isr_cookie)),"1" ((_enable_mask)) \
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); \
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}
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#define _CPU_ISR_Flash( _isr_cookie ) \
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{ register u32 _flash_mask = 0; \
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__asm__ __volatile__ ( \
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" cmpwi %0,0\n" \
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" beq 1f\n" \
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" mfmsr %1\n" \
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" ori %1,%1,0x8000\n" \
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" mtmsr %1\n" \
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" rlwinm %1,%1,0,17,15\n" \
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" mtmsr %1\n" \
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"1:" \
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: "=r" ((_isr_cookie)), "=&r" ((_flash_mask)) \
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: "0" ((_isr_cookie)), "1" ((_flash_mask)) \
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); \
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}
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#define _CPU_FPR_Enable() \
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{ register u32 _val = 0; \
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asm volatile ("mfmsr %0; ori %0,%0,0x2000; mtmsr %0" : \
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"=&r" (_val) : "0" (_val));\
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}
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#define _CPU_FPR_Disable() \
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{ register u32 _val = 0; \
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asm volatile ("mfmsr %0; rlwinm %0,%0,0,19,17; mtmsr %0" : \
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"=&r" (_val) : "0" (_val));\
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}
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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static inline u16 bswap16(u16 val)
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{
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u16 tmp = val;
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return __lhbrx(&tmp,0);
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}
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static inline u32 bswap32(u32 val)
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{
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u32 tmp = val;
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return __lwbrx(&tmp,0);
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}
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static inline u64 bswap64(u64 val)
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{
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union ullc {
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u64 ull;
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u32 ul[2];
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} outv;
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u64 tmp = val;
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outv.ul[0] = __lwbrx(&tmp,4);
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outv.ul[1] = __lwbrx(&tmp,0);
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return outv.ull;
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}
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// Basic I/O
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static inline u32 read32(u32 addr)
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{
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u32 x;
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asm volatile("lwz %0,0(%1) ; sync" : "=r"(x) : "b"(0xc0000000 | addr));
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return x;
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}
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static inline void write32(u32 addr, u32 x)
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{
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asm("stw %0,0(%1) ; eieio" : : "r"(x), "b"(0xc0000000 | addr));
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}
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static inline void mask32(u32 addr, u32 clear, u32 set)
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{
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write32(addr, (read32(addr)&(~clear)) | set);
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}
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static inline u16 read16(u32 addr)
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{
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u16 x;
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asm volatile("lhz %0,0(%1) ; sync" : "=r"(x) : "b"(0xc0000000 | addr));
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return x;
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}
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static inline void write16(u32 addr, u16 x)
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{
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asm("sth %0,0(%1) ; eieio" : : "r"(x), "b"(0xc0000000 | addr));
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}
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static inline u8 read8(u32 addr)
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{
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u8 x;
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asm volatile("lbz %0,0(%1) ; sync" : "=r"(x) : "b"(0xc0000000 | addr));
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return x;
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}
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static inline void write8(u32 addr, u8 x)
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{
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asm("stb %0,0(%1) ; eieio" : : "r"(x), "b"(0xc0000000 | addr));
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}
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static inline void writef32(u32 addr, f32 x)
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{
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asm("stfs %0,0(%1) ; eieio" : : "f"(x), "b"(0xc0000000 | addr));
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}
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif
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