mirror of
https://github.com/serge1/ELFIO.git
synced 2024-12-27 12:17:28 +00:00
Add RISC-V relocation types
This commit is contained in:
parent
182248f364
commit
e361316ce4
@ -955,6 +955,58 @@ constexpr unsigned R_AARCH64_TLS_DTPREL64 = 1029;
|
|||||||
constexpr unsigned R_AARCH64_TLS_TPREL = 1030;
|
constexpr unsigned R_AARCH64_TLS_TPREL = 1030;
|
||||||
constexpr unsigned R_AARCH64_TLS_TPREL64 = 1030;
|
constexpr unsigned R_AARCH64_TLS_TPREL64 = 1030;
|
||||||
constexpr unsigned R_AARCH64_TLSDESC = 1031;
|
constexpr unsigned R_AARCH64_TLSDESC = 1031;
|
||||||
|
// RISC-V
|
||||||
|
constexpr unsigned R_RISCV_NONE = 0;
|
||||||
|
constexpr unsigned R_RISCV_32 = 1;
|
||||||
|
constexpr unsigned R_RISCV_64 = 2;
|
||||||
|
constexpr unsigned R_RISCV_RELATIVE = 3;
|
||||||
|
constexpr unsigned R_RISCV_COPY = 4;
|
||||||
|
constexpr unsigned R_RISCV_JUMP_SLOT = 5;
|
||||||
|
constexpr unsigned R_RISCV_TLS_DTPMOD32 = 6;
|
||||||
|
constexpr unsigned R_RISCV_TLS_DTPMOD64 = 7;
|
||||||
|
constexpr unsigned R_RISCV_TLS_DTPREL32 = 8;
|
||||||
|
constexpr unsigned R_RISCV_TLS_DTPREL64 = 9;
|
||||||
|
constexpr unsigned R_RISCV_TLS_TPREL32 = 10;
|
||||||
|
constexpr unsigned R_RISCV_TLS_TPREL64 = 11;
|
||||||
|
constexpr unsigned R_RISCV_BRANCH = 16;
|
||||||
|
constexpr unsigned R_RISCV_JAL = 17;
|
||||||
|
constexpr unsigned R_RISCV_CALL = 18;
|
||||||
|
constexpr unsigned R_RISCV_CALL_PLT = 19;
|
||||||
|
constexpr unsigned R_RISCV_GOT_HI20 = 20;
|
||||||
|
constexpr unsigned R_RISCV_TLS_GOT_HI20 = 21;
|
||||||
|
constexpr unsigned R_RISCV_TLS_GD_HI20 = 22;
|
||||||
|
constexpr unsigned R_RISCV_PCREL_HI20 = 23;
|
||||||
|
constexpr unsigned R_RISCV_PCREL_LO12_I = 24;
|
||||||
|
constexpr unsigned R_RISCV_PCREL_LO12_S = 25;
|
||||||
|
constexpr unsigned R_RISCV_HI20 = 26;
|
||||||
|
constexpr unsigned R_RISCV_LO12_I = 27;
|
||||||
|
constexpr unsigned R_RISCV_LO12_S = 28;
|
||||||
|
constexpr unsigned R_RISCV_TPREL_HI20 = 29;
|
||||||
|
constexpr unsigned R_RISCV_TPREL_LO12_I = 30;
|
||||||
|
constexpr unsigned R_RISCV_TPREL_LO12_S = 31;
|
||||||
|
constexpr unsigned R_RISCV_TPREL_ADD = 32;
|
||||||
|
constexpr unsigned R_RISCV_ADD8 = 33;
|
||||||
|
constexpr unsigned R_RISCV_ADD16 = 34;
|
||||||
|
constexpr unsigned R_RISCV_ADD32 = 35;
|
||||||
|
constexpr unsigned R_RISCV_ADD64 = 36;
|
||||||
|
constexpr unsigned R_RISCV_SUB8 = 37;
|
||||||
|
constexpr unsigned R_RISCV_SUB16 = 38;
|
||||||
|
constexpr unsigned R_RISCV_SUB32 = 39;
|
||||||
|
constexpr unsigned R_RISCV_SUB64 = 40;
|
||||||
|
constexpr unsigned R_RISCV_GNU_VTINHERIT = 41;
|
||||||
|
constexpr unsigned R_RISCV_GNU_VTENTRY = 42;
|
||||||
|
constexpr unsigned R_RISCV_ALIGN = 43;
|
||||||
|
constexpr unsigned R_RISCV_RVC_BRANCH = 44;
|
||||||
|
constexpr unsigned R_RISCV_RVC_JUMP = 45;
|
||||||
|
constexpr unsigned R_RISCV_RVC_LUI = 46;
|
||||||
|
constexpr unsigned R_RISCV_RELAX = 51;
|
||||||
|
constexpr unsigned R_RISCV_SUB6 = 52;
|
||||||
|
constexpr unsigned R_RISCV_SET6 = 53;
|
||||||
|
constexpr unsigned R_RISCV_SET8 = 54;
|
||||||
|
constexpr unsigned R_RISCV_SET16 = 55;
|
||||||
|
constexpr unsigned R_RISCV_SET32 = 56;
|
||||||
|
constexpr unsigned R_RISCV_32_PCREL = 57;
|
||||||
|
constexpr unsigned R_RISCV_IRELATIVE = 58;
|
||||||
|
|
||||||
// Segment types
|
// Segment types
|
||||||
constexpr Elf_Word PT_NULL = 0;
|
constexpr Elf_Word PT_NULL = 0;
|
||||||
|
Loading…
Reference in New Issue
Block a user