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In spite of the previous commit, clang-formatter inserts multi-line comments.

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This is an attempt to avoid this
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Serge Lamikhov-Center 2021-01-19 09:37:18 +02:00
parent 8ab497c57b
commit 7e9c0a4675
1 changed files with 183 additions and 187 deletions
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34
elfio/elf_types.hpp
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@ -92,8 +92,7 @@ typedef uint64_t Elf64_Off;
#define EM_860 7 // Intel 80860 #define EM_860 7 // Intel 80860
#define EM_MIPS 8 // MIPS R3000 (officially, big-endian only) #define EM_MIPS 8 // MIPS R3000 (officially, big-endian only)
#define EM_S370 9 // IBM System/370 #define EM_S370 9 // IBM System/370
#define EM_MIPS_RS3_LE \ #define EM_MIPS_RS3_LE 10 // MIPS R3000 little-endian (Deprecated)
10 // MIPS R3000 little-endian (Oct 4 1999 Draft) Deprecated
#define EM_res011 11 // Reserved #define EM_res011 11 // Reserved
#define EM_res012 12 // Reserved #define EM_res012 12 // Reserved
#define EM_res013 13 // Reserved #define EM_res013 13 // Reserved
@ -194,8 +193,7 @@ typedef uint64_t Elf64_Off;
#define EM_SE_C33 107 // S1C33 Family of Seiko Epson processors #define EM_SE_C33 107 // S1C33 Family of Seiko Epson processors
#define EM_SEP 108 // Sharp embedded microprocessor #define EM_SEP 108 // Sharp embedded microprocessor
#define EM_ARCA 109 // Arca RISC Microprocessor #define EM_ARCA 109 // Arca RISC Microprocessor
#define EM_UNICORE \ #define EM_UNICORE 110 // Microprocessor series from PKU-Unity Ltd.
110 // Microprocessor series from PKU-Unity Ltd. and MPRC of Peking University
#define EM_EXCESS 111 // eXcess: 16/32/64-bit configurable embedded CPU #define EM_EXCESS 111 // eXcess: 16/32/64-bit configurable embedded CPU
#define EM_DXP 112 // Icera Semiconductor Inc. Deep Execution Processor #define EM_DXP 112 // Icera Semiconductor Inc. Deep Execution Processor
#define EM_ALTERA_NIOS2 113 // Altera Nios II soft-core processor #define EM_ALTERA_NIOS2 113 // Altera Nios II soft-core processor
@ -203,8 +201,7 @@ typedef uint64_t Elf64_Off;
#define EM_XGATE 115 // Motorola XGATE embedded processor #define EM_XGATE 115 // Motorola XGATE embedded processor
#define EM_C166 116 // Infineon C16x/XC16x processor #define EM_C166 116 // Infineon C16x/XC16x processor
#define EM_M16C 117 // Renesas M16C series microprocessors #define EM_M16C 117 // Renesas M16C series microprocessors
#define EM_DSPIC30F \ #define EM_DSPIC30F 118 // Microchip Technology dsPIC30F DSignal Controller
118 // Microchip Technology dsPIC30F Digital Signal Controller
#define EM_CE 119 // Freescale Communication Engine RISC core #define EM_CE 119 // Freescale Communication Engine RISC core
#define EM_M32C 120 // Renesas M32C series microprocessors #define EM_M32C 120 // Renesas M32C series microprocessors
#define EM_res121 121 // Reserved #define EM_res121 121 // Reserved
@ -254,8 +251,7 @@ typedef uint64_t Elf64_Off;
#define EM_QDSP6 164 // QUALCOMM DSP6 Processor #define EM_QDSP6 164 // QUALCOMM DSP6 Processor
#define EM_8051 165 // Intel 8051 and variants #define EM_8051 165 // Intel 8051 and variants
#define EM_STXP7X 166 // STMicroelectronics STxP7x family #define EM_STXP7X 166 // STMicroelectronics STxP7x family
#define EM_NDS32 \ #define EM_NDS32 167 // Andes Technology embedded RISC processor family
167 // Andes Technology compact code size embedded RISC processor family
#define EM_ECOG1 168 // Cyan Technology eCOG1X family #define EM_ECOG1 168 // Cyan Technology eCOG1X family
#define EM_ECOG1X 168 // Cyan Technology eCOG1X family #define EM_ECOG1X 168 // Cyan Technology eCOG1X family
#define EM_MAXQ30 169 // Dallas Semiconductor MAXQ30 Core Micro-controllers #define EM_MAXQ30 169 // Dallas Semiconductor MAXQ30 Core Micro-controllers
@ -393,22 +389,22 @@ typedef uint64_t Elf64_Off;
#define ELFOSABI_NSK 14 // Hewlett-Packard Non-Stop Kernel #define ELFOSABI_NSK 14 // Hewlett-Packard Non-Stop Kernel
#define ELFOSABI_AROS 15 // Amiga Research OS #define ELFOSABI_AROS 15 // Amiga Research OS
#define ELFOSABI_FENIXOS 16 // The FenixOS highly scalable multi-core OS #define ELFOSABI_FENIXOS 16 // The FenixOS highly scalable multi-core OS
// 64-255 Architecture-specific value range // 64-255 Architecture-specific value range
#define ELFOSABI_AMDGPU_HSA \ // AMDGPU OS for HSA compatible compute kernels
64 // AMDGPU OS for HSA compatible compute #define ELFOSABI_AMDGPU_HSA 64
// kernels. // AMDGPU OS for AMD PAL compatible graphics
#define ELFOSABI_AMDGPU_PAL \ // shaders and compute kernels
65 // AMDGPU OS for AMD PAL compatible graphics #define ELFOSABI_AMDGPU_PAL 65
// shaders and compute kernels. // AMDGPU OS for Mesa3D compatible graphics
#define ELFOSABI_AMDGPU_MESA3D \ // shaders and compute kernels
66 // AMDGPU OS for Mesa3D compatible graphics #define ELFOSABI_AMDGPU_MESA3D 66
// shaders and compute kernels.
// AMDGPU specific e_flags // AMDGPU specific e_flags
#define EF_AMDGPU_MACH 0x0ff // AMDGPU processor selection mask. #define EF_AMDGPU_MACH 0x0ff // AMDGPU processor selection mask.
#define EF_AMDGPU_XNACK \ // Indicates if the XNACK target feature is
0x100 // Indicates if the XNACK target feature is
// enabled for all code contained in the ELF. // enabled for all code contained in the ELF.
#define EF_AMDGPU_XNACK 0x100
// AMDGPU processors // AMDGPU processors
#define EF_AMDGPU_MACH_NONE 0x000 // Unspecified processor. #define EF_AMDGPU_MACH_NONE 0x000 // Unspecified processor.
#define EF_AMDGPU_MACH_R600_R600 0x001 #define EF_AMDGPU_MACH_R600_R600 0x001