mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-18 08:11:21 +00:00
636 lines
29 KiB
C++
636 lines
29 KiB
C++
/*
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* Copyright (c) 2018 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <switch.h>
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#include "dmnt_cheat_types.hpp"
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#include "dmnt_cheat_vm.hpp"
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#include "dmnt_cheat_manager.hpp"
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#include "dmnt_hid.hpp"
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void DmntCheatVm::OpenDebugLogFile() {
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#ifdef DMNT_CHEAT_VM_DEBUG_LOG
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CloseDebugLogFile();
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this->debug_log_file = fopen("cheat_vm_log.txt", "wb");
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#endif
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}
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void DmntCheatVm::CloseDebugLogFile() {
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#ifdef DMNT_CHEAT_VM_DEBUG_LOG
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if (this->debug_log_file != NULL) {
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fclose(this->debug_log_file);
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this->debug_log_file = NULL;
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}
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#endif
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}
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void DmntCheatVm::LogToDebugFile(const char *format, ...) {
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#ifdef DMNT_CHEAT_VM_DEBUG_LOG
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if (this->debug_log_file != NULL) {
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va_list arglist;
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va_start(arglist, format);
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vfprintf(this->debug_log_file, format, arglist);
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va_end(arglist);
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}
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#endif
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}
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void DmntCheatVm::LogOpcode(const CheatVmOpcode *opcode) {
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#ifndef DMNT_CHEAT_VM_DEBUG_LOG
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return;
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#endif
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switch (opcode->opcode) {
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case CheatVmOpcodeType_StoreStatic:
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this->LogToDebugFile("Opcode: Store Static\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->store_static.bit_width);
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this->LogToDebugFile("Mem Type: %x\n", opcode->store_static.mem_type);
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this->LogToDebugFile("Reg Idx: %x\n", opcode->store_static.offset_register);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->store_static.rel_address);
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this->LogToDebugFile("Value: %lx\n", opcode->store_static.value.bit64);
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break;
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case CheatVmOpcodeType_BeginConditionalBlock:
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this->LogToDebugFile("Opcode: Begin Conditional\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->begin_cond.bit_width);
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this->LogToDebugFile("Mem Type: %x\n", opcode->begin_cond.mem_type);
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this->LogToDebugFile("Cond Type: %x\n", opcode->begin_cond.cond_type);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->begin_cond.rel_address);
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this->LogToDebugFile("Value: %lx\n", opcode->begin_cond.value.bit64);
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break;
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case CheatVmOpcodeType_EndConditionalBlock:
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this->LogToDebugFile("Opcode: End Conditional\n");
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break;
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case CheatVmOpcodeType_ControlLoop:
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if (opcode->ctrl_loop.start_loop) {
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this->LogToDebugFile("Opcode: Start Loop\n");
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this->LogToDebugFile("Reg Idx: %x\n", opcode->ctrl_loop.reg_index);
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this->LogToDebugFile("Num Iters: %x\n", opcode->ctrl_loop.num_iters);
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} else {
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this->LogToDebugFile("Opcode: End Loop\n");
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this->LogToDebugFile("Reg Idx: %x\n", opcode->ctrl_loop.reg_index);
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}
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break;
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case CheatVmOpcodeType_LoadRegisterStatic:
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this->LogToDebugFile("Opcode: Load Register Static\n");
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this->LogToDebugFile("Reg Idx: %x\n", opcode->ldr_static.reg_index);
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this->LogToDebugFile("Value: %lx\n", opcode->ldr_static.value);
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break;
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case CheatVmOpcodeType_LoadRegisterMemory:
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this->LogToDebugFile("Opcode: Load Register Memory\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->ldr_memory.bit_width);
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this->LogToDebugFile("Reg Idx: %x\n", opcode->ldr_memory.reg_index);
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this->LogToDebugFile("Mem Type: %x\n", opcode->ldr_memory.mem_type);
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this->LogToDebugFile("From Reg: %d\n", opcode->ldr_memory.load_from_reg);
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this->LogToDebugFile("Rel Addr: %lx\n", opcode->ldr_memory.rel_address);
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break;
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case CheatVmOpcodeType_StoreToRegisterAddress:
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this->LogToDebugFile("Opcode: Store Static to Register Address\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->str_regaddr.bit_width);
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this->LogToDebugFile("Reg Idx: %x\n", opcode->str_regaddr.reg_index);
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if (opcode->str_regaddr.add_offset_reg) {
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this->LogToDebugFile("O Reg Idx: %x\n", opcode->str_regaddr.offset_reg_index);
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}
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this->LogToDebugFile("Incr Reg: %d\n", opcode->str_regaddr.increment_reg);
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this->LogToDebugFile("Value: %lx\n", opcode->str_regaddr.value);
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break;
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case CheatVmOpcodeType_PerformArithmeticStatic:
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this->LogToDebugFile("Opcode: Perform Static Arithmetic\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->perform_math_static.bit_width);
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this->LogToDebugFile("Reg Idx: %x\n", opcode->perform_math_static.reg_index);
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this->LogToDebugFile("Math Type: %x\n", opcode->perform_math_static.math_type);
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this->LogToDebugFile("Value: %lx\n", opcode->perform_math_static.value);
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break;
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case CheatVmOpcodeType_BeginKeypressConditionalBlock:
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this->LogToDebugFile("Opcode: Begin Keypress Conditional\n");
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this->LogToDebugFile("Key Mask: %x\n", opcode->begin_keypress_cond.key_mask);
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break;
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case CheatVmOpcodeType_PerformArithmeticRegister:
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this->LogToDebugFile("Opcode: Perform Register Arithmetic\n");
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this->LogToDebugFile("Bit Width: %x\n", opcode->perform_math_reg.bit_width);
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this->LogToDebugFile("Dst Idx: %x\n", opcode->perform_math_reg.dst_reg_index);
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this->LogToDebugFile("Src1 Idx: %x\n", opcode->perform_math_reg.src_reg_1_index);
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if (opcode->perform_math_reg.has_immediate) {
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this->LogToDebugFile("Value: %lx\n", opcode->perform_math_reg.value.bit64);
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} else {
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this->LogToDebugFile("Src2 Idx: %x\n", opcode->perform_math_reg.src_reg_2_index);
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}
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break;
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default:
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this->LogToDebugFile("Unknown opcode: %x\n", opcode->opcode);
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break;
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}
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}
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bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode *out) {
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/* If we've ever seen a decode failure, return false. */
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bool valid = this->decode_success;
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CheatVmOpcode opcode = {};
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ON_SCOPE_EXIT {
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this->decode_success &= valid;
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if (valid) {
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*out = opcode;
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}
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};
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/* Helper function for getting instruction dwords. */
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auto GetNextDword = [&]() {
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if (this->instruction_ptr >= this->num_opcodes) {
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valid = false;
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return static_cast<u32>(0);
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}
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return this->program[this->instruction_ptr++];
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};
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/* Helper function for parsing a VmInt. */
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auto GetNextVmInt = [&](const u32 bit_width) {
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VmInt val = {0};
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const u32 first_dword = GetNextDword();
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switch (bit_width) {
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case 1:
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val.bit8 = (u8)first_dword;
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break;
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case 2:
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val.bit16 = (u16)first_dword;
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break;
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case 4:
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val.bit32 = first_dword;
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break;
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case 8:
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val.bit64 = (((u64)first_dword) << 32ul) | ((u64)GetNextDword());
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break;
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}
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return val;
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};
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/* Read opcode. */
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const u32 first_dword = GetNextDword();
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if (!valid) {
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return valid;
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}
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opcode.opcode = (CheatVmOpcodeType)(((first_dword >> 28) & 0xF));
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switch (opcode.opcode) {
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case CheatVmOpcodeType_StoreStatic:
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{
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/* 0TMR00AA AAAAAAAA YYYYYYYY (YYYYYYYY) */
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/* Read additional words. */
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const u32 second_dword = GetNextDword();
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opcode.store_static.bit_width = (first_dword >> 24) & 0xF;
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opcode.store_static.mem_type = (MemoryAccessType)((first_dword >> 20) & 0xF);
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opcode.store_static.offset_register = ((first_dword >> 16) & 0xF);
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opcode.store_static.rel_address = ((u64)(first_dword & 0xFF) << 32ul) | ((u64)second_dword);
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opcode.store_static.value = GetNextVmInt(opcode.store_static.bit_width);
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}
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break;
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case CheatVmOpcodeType_BeginConditionalBlock:
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{
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/* 1TMC00AA AAAAAAAA YYYYYYYY (YYYYYYYY) */
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/* Read additional words. */
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const u32 second_dword = GetNextDword();
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opcode.begin_cond.bit_width = (first_dword >> 24) & 0xF;
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opcode.begin_cond.mem_type = (MemoryAccessType)((first_dword >> 20) & 0xF);
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opcode.begin_cond.cond_type = (ConditionalComparisonType)((first_dword >> 16) & 0xF);
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opcode.begin_cond.rel_address = ((u64)(first_dword & 0xFF) << 32ul) | ((u64)second_dword);
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opcode.begin_cond.value = GetNextVmInt(opcode.store_static.bit_width);
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}
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break;
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case CheatVmOpcodeType_EndConditionalBlock:
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{
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/* 20000000 */
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/* There's actually nothing left to process here! */
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}
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break;
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case CheatVmOpcodeType_ControlLoop:
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{
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/* 300R0000 VVVVVVVV */
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/* 310R0000 */
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/* Parse register, whether loop start or loop end. */
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opcode.ctrl_loop.start_loop = ((first_dword >> 24) & 0xF) == 0;
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opcode.ctrl_loop.reg_index = ((first_dword >> 20) & 0xF);
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/* Read number of iters if loop start. */
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if (opcode.ctrl_loop.start_loop) {
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opcode.ctrl_loop.num_iters = GetNextDword();
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}
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}
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break;
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case CheatVmOpcodeType_LoadRegisterStatic:
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{
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/* 400R0000 VVVVVVVV VVVVVVVV */
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/* Read additional words. */
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opcode.ldr_static.reg_index = ((first_dword >> 20) & 0xF);
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opcode.ldr_static.value = (((u64)GetNextDword()) << 32ul) | ((u64)GetNextDword());
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}
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break;
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case CheatVmOpcodeType_LoadRegisterMemory:
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{
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/* 5TMRI0AA AAAAAAAA */
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/* Read additional words. */
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const u32 second_dword = GetNextDword();
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opcode.ldr_memory.bit_width = (first_dword >> 24) & 0xF;
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opcode.ldr_memory.mem_type = (MemoryAccessType)((first_dword >> 20) & 0xF);
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opcode.ldr_memory.reg_index = ((first_dword >> 16) & 0xF);
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opcode.ldr_memory.load_from_reg = ((first_dword >> 12) & 0xF) != 0;
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opcode.ldr_memory.rel_address = ((u64)(first_dword & 0xFF) << 32ul) | ((u64)second_dword);
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}
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break;
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case CheatVmOpcodeType_StoreToRegisterAddress:
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{
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/* 6T0RIor0 VVVVVVVV VVVVVVVV */
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/* Read additional words. */
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opcode.str_regaddr.bit_width = (first_dword >> 24) & 0xF;
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opcode.str_regaddr.reg_index = ((first_dword >> 16) & 0xF);
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opcode.str_regaddr.increment_reg = ((first_dword >> 12) & 0xF) != 0;
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opcode.str_regaddr.add_offset_reg = ((first_dword >> 8) & 0xF) != 0;
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opcode.str_regaddr.offset_reg_index = ((first_dword >> 4) & 0xF);
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opcode.str_regaddr.value = (((u64)GetNextDword()) << 32ul) | ((u64)GetNextDword());
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}
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break;
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case CheatVmOpcodeType_PerformArithmeticStatic:
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{
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/* 7T0RC000 VVVVVVVV */
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/* Read additional words. */
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opcode.perform_math_static.bit_width = (first_dword >> 24) & 0xF;
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opcode.perform_math_static.reg_index = ((first_dword >> 16) & 0xF);
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opcode.perform_math_static.math_type = (RegisterArithmeticType)((first_dword >> 12) & 0xF);
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opcode.perform_math_static.value = GetNextDword();
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}
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break;
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case CheatVmOpcodeType_BeginKeypressConditionalBlock:
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{
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/* 8kkkkkkk */
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/* Just parse the mask. */
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opcode.begin_keypress_cond.key_mask = first_dword & 0x0FFFFFFF;
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}
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break;
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case CheatVmOpcodeType_PerformArithmeticRegister:
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{
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/* 9TCRSIs0 (VVVVVVVV (VVVVVVVV)) */
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opcode.perform_math_reg.bit_width = (first_dword >> 24) & 0xF;
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opcode.perform_math_reg.math_type = (RegisterArithmeticType)((first_dword >> 20) & 0xF);
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opcode.perform_math_reg.dst_reg_index = ((first_dword >> 16) & 0xF);
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opcode.perform_math_reg.src_reg_1_index = ((first_dword >> 12) & 0xF);
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opcode.perform_math_reg.has_immediate = ((first_dword >> 8) & 0xF) != 0;
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if (opcode.perform_math_reg.has_immediate) {
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opcode.perform_math_reg.src_reg_2_index = 0;
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opcode.perform_math_reg.value = GetNextVmInt(opcode.perform_math_reg.bit_width);
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} else {
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opcode.perform_math_reg.src_reg_2_index = ((first_dword >> 4) & 0xF);
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}
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}
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break;
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default:
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/* Unrecognized instruction cannot be decoded. */
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valid = false;
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break;
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}
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/* End decoding. */
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return valid;
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}
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void DmntCheatVm::SkipConditionalBlock() {
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CheatVmOpcode skip_opcode;
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while (this->DecodeNextOpcode(&skip_opcode)) {
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/* Decode instructions until we see end of conditional block. */
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/* NOTE: This is broken in gateway's implementation. */
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/* Gateway currently checks for "0x2" instead of "0x20000000" */
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/* In addition, they do a linear scan instead of correctly decoding opcodes. */
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/* This causes issues if "0x2" appears as an immediate in the conditional block... */
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if (skip_opcode.opcode == CheatVmOpcodeType_EndConditionalBlock) {
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break;
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}
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}
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}
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u64 DmntCheatVm::GetVmInt(VmInt value, u32 bit_width) {
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switch (bit_width) {
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case 1:
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return value.bit8;
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case 2:
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return value.bit16;
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case 4:
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return value.bit32;
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case 8:
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return value.bit64;
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default:
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/* Invalid bit width -> return 0. */
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return 0;
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}
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}
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u64 DmntCheatVm::GetCheatProcessAddress(const CheatProcessMetadata* metadata, MemoryAccessType mem_type, u64 rel_address) {
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switch (mem_type) {
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case MemoryAccessType_MainNso:
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default:
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return metadata->main_nso_extents.base + rel_address;
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case MemoryAccessType_Heap:
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return metadata->heap_extents.base + rel_address;
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}
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}
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void DmntCheatVm::ResetState() {
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for (size_t i = 0; i < DmntCheatVm::NumRegisters; i++) {
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this->registers[i] = 0;
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this->loop_tops[i] = 0;
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}
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this->instruction_ptr = 0;
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this->decode_success = true;
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}
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bool DmntCheatVm::LoadProgram(const CheatEntry *cheats, size_t num_cheats) {
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/* Reset opcode count. */
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this->num_opcodes = 0;
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for (size_t i = 0; i < num_cheats; i++) {
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if (cheats[i].enabled) {
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/* Bounds check. */
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if (cheats[i].definition.num_opcodes + this->num_opcodes > MaximumProgramOpcodeCount) {
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return false;
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}
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for (size_t n = 0; n < cheats[i].definition.num_opcodes; n++) {
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this->program[this->num_opcodes++] = cheats[i].definition.opcodes[n];
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}
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}
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}
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return true;
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}
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void DmntCheatVm::Execute(const CheatProcessMetadata *metadata) {
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CheatVmOpcode cur_opcode;
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u64 kDown = 0;
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/* Get Keys down. */
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HidManagement::GetKeysDown(&kDown);
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this->OpenDebugLogFile();
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ON_SCOPE_EXIT { this->CloseDebugLogFile(); };
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this->LogToDebugFile("Started VM execution.\n");
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this->LogToDebugFile("Main NSO: %012lx\n", metadata->main_nso_extents.base);
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this->LogToDebugFile("Heap: %012lx\n", metadata->main_nso_extents.base);
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this->LogToDebugFile("Keys Down: %08x\n", (u32)(kDown & 0x0FFFFFFF));
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/* Clear VM state. */
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this->ResetState();
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/* Loop until program finishes. */
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while (this->DecodeNextOpcode(&cur_opcode)) {
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this->LogToDebugFile("Instruction Ptr: %04x\n", (u32)this->instruction_ptr);
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for (size_t i = 0; i < NumRegisters; i++) {
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this->LogToDebugFile("Registers[%02x]: %016lx\n", i, this->registers[i]);
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}
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this->LogOpcode(&cur_opcode);
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switch (cur_opcode.opcode) {
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case CheatVmOpcodeType_StoreStatic:
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{
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/* Calculate address, write value to memory. */
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u64 dst_address = GetCheatProcessAddress(metadata, cur_opcode.store_static.mem_type, cur_opcode.store_static.rel_address + this->registers[cur_opcode.store_static.offset_register]);
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u64 dst_value = GetVmInt(cur_opcode.store_static.value, cur_opcode.store_static.bit_width);
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switch (cur_opcode.store_static.bit_width) {
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case 1:
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case 2:
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case 4:
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case 8:
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DmntCheatManager::WriteCheatProcessMemoryForVm(dst_address, &dst_value, cur_opcode.store_static.bit_width);
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break;
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}
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}
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break;
|
|
case CheatVmOpcodeType_BeginConditionalBlock:
|
|
{
|
|
/* Read value from memory. */
|
|
u64 src_address = GetCheatProcessAddress(metadata, cur_opcode.begin_cond.mem_type, cur_opcode.begin_cond.rel_address);
|
|
u64 src_value = 0;
|
|
switch (cur_opcode.store_static.bit_width) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
DmntCheatManager::ReadCheatProcessMemoryForVm(src_address, &src_value, cur_opcode.begin_cond.bit_width);
|
|
break;
|
|
}
|
|
/* Check against condition. */
|
|
u64 cond_value = GetVmInt(cur_opcode.begin_cond.value, cur_opcode.begin_cond.bit_width);
|
|
bool cond_met = false;
|
|
switch (cur_opcode.begin_cond.cond_type) {
|
|
case ConditionalComparisonType_GT:
|
|
cond_met = src_value > cond_value;
|
|
break;
|
|
case ConditionalComparisonType_GE:
|
|
cond_met = src_value >= cond_value;
|
|
break;
|
|
case ConditionalComparisonType_LT:
|
|
cond_met = src_value < cond_value;
|
|
break;
|
|
case ConditionalComparisonType_LE:
|
|
cond_met = src_value <= cond_value;
|
|
break;
|
|
case ConditionalComparisonType_EQ:
|
|
cond_met = src_value == cond_value;
|
|
break;
|
|
case ConditionalComparisonType_NE:
|
|
cond_met = src_value != cond_value;
|
|
break;
|
|
}
|
|
/* Skip conditional block if condition not met. */
|
|
if (!cond_met) {
|
|
this->SkipConditionalBlock();
|
|
}
|
|
}
|
|
break;
|
|
case CheatVmOpcodeType_EndConditionalBlock:
|
|
/* There is nothing to do here. Just move on to the next instruction. */
|
|
break;
|
|
case CheatVmOpcodeType_ControlLoop:
|
|
if (cur_opcode.ctrl_loop.start_loop) {
|
|
/* Start a loop. */
|
|
this->registers[cur_opcode.ctrl_loop.reg_index] = cur_opcode.ctrl_loop.num_iters;
|
|
this->loop_tops[cur_opcode.ctrl_loop.reg_index] = this->instruction_ptr;
|
|
} else {
|
|
/* End a loop. */
|
|
this->registers[cur_opcode.ctrl_loop.reg_index]--;
|
|
if (this->registers[cur_opcode.ctrl_loop.reg_index] != 0) {
|
|
this->instruction_ptr = this->loop_tops[cur_opcode.ctrl_loop.reg_index];
|
|
}
|
|
}
|
|
break;
|
|
case CheatVmOpcodeType_LoadRegisterStatic:
|
|
/* Set a register to a static value. */
|
|
this->registers[cur_opcode.ldr_static.reg_index] = cur_opcode.ldr_static.value;
|
|
break;
|
|
case CheatVmOpcodeType_LoadRegisterMemory:
|
|
{
|
|
/* Choose source address. */
|
|
u64 src_address;
|
|
if (cur_opcode.ldr_memory.load_from_reg) {
|
|
src_address = this->registers[cur_opcode.ldr_memory.reg_index] + cur_opcode.ldr_memory.rel_address;
|
|
} else {
|
|
src_address = GetCheatProcessAddress(metadata, cur_opcode.ldr_memory.mem_type, cur_opcode.ldr_memory.rel_address);
|
|
}
|
|
/* Read into register. Gateway only reads on valid bitwidth. */
|
|
switch (cur_opcode.ldr_memory.bit_width) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
DmntCheatManager::ReadCheatProcessMemoryForVm(src_address, &this->registers[cur_opcode.ldr_memory.reg_index], cur_opcode.ldr_memory.bit_width);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case CheatVmOpcodeType_StoreToRegisterAddress:
|
|
{
|
|
/* Calculate address. */
|
|
u64 dst_address = this->registers[cur_opcode.str_regaddr.reg_index];
|
|
u64 dst_value = cur_opcode.str_regaddr.value;
|
|
if (cur_opcode.str_regaddr.add_offset_reg) {
|
|
dst_address += this->registers[cur_opcode.str_regaddr.offset_reg_index];
|
|
}
|
|
/* Write value to memory. Gateway only writes on valid bitwidth. */
|
|
switch (cur_opcode.str_regaddr.bit_width) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
DmntCheatManager::WriteCheatProcessMemoryForVm(dst_address, &dst_value, cur_opcode.str_regaddr.bit_width);
|
|
break;
|
|
}
|
|
/* Increment register if relevant. */
|
|
if (cur_opcode.str_regaddr.increment_reg) {
|
|
this->registers[cur_opcode.str_regaddr.reg_index] += cur_opcode.str_regaddr.bit_width;
|
|
}
|
|
}
|
|
break;
|
|
case CheatVmOpcodeType_PerformArithmeticStatic:
|
|
{
|
|
/* Do requested math. */
|
|
switch (cur_opcode.perform_math_static.math_type) {
|
|
case RegisterArithmeticType_Addition:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] += (u64)cur_opcode.perform_math_static.value;
|
|
break;
|
|
case RegisterArithmeticType_Subtraction:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] -= (u64)cur_opcode.perform_math_static.value;
|
|
break;
|
|
case RegisterArithmeticType_Multiplication:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] *= (u64)cur_opcode.perform_math_static.value;
|
|
break;
|
|
case RegisterArithmeticType_LeftShift:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] <<= (u64)cur_opcode.perform_math_static.value;
|
|
break;
|
|
case RegisterArithmeticType_RightShift:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] >>= (u64)cur_opcode.perform_math_static.value;
|
|
break;
|
|
default:
|
|
/* Do not handle extensions here. */
|
|
break;
|
|
}
|
|
/* Apply bit width. */
|
|
switch (cur_opcode.perform_math_static.bit_width) {
|
|
case 1:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] = static_cast<u8>(this->registers[cur_opcode.perform_math_static.reg_index]);
|
|
break;
|
|
case 2:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] = static_cast<u16>(this->registers[cur_opcode.perform_math_static.reg_index]);
|
|
break;
|
|
case 4:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] = static_cast<u32>(this->registers[cur_opcode.perform_math_static.reg_index]);
|
|
break;
|
|
case 8:
|
|
this->registers[cur_opcode.perform_math_static.reg_index] = static_cast<u64>(this->registers[cur_opcode.perform_math_static.reg_index]);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case CheatVmOpcodeType_BeginKeypressConditionalBlock:
|
|
/* Check for keypress. */
|
|
if ((cur_opcode.begin_keypress_cond.key_mask & kDown) != cur_opcode.begin_keypress_cond.key_mask) {
|
|
/* Keys not pressed. Skip conditional block. */
|
|
this->SkipConditionalBlock();
|
|
}
|
|
break;
|
|
case CheatVmOpcodeType_PerformArithmeticRegister:
|
|
{
|
|
const u64 operand_1_value = this->registers[cur_opcode.perform_math_reg.src_reg_1_index];
|
|
const u64 operand_2_value = cur_opcode.perform_math_reg.has_immediate ?
|
|
GetVmInt(cur_opcode.perform_math_reg.value, cur_opcode.perform_math_reg.bit_width) :
|
|
this->registers[cur_opcode.perform_math_reg.src_reg_2_index];
|
|
|
|
u64 res_val = 0;
|
|
/* Do requested math. */
|
|
switch (cur_opcode.perform_math_reg.math_type) {
|
|
case RegisterArithmeticType_Addition:
|
|
res_val = operand_1_value + operand_2_value;
|
|
break;
|
|
case RegisterArithmeticType_Subtraction:
|
|
res_val = operand_1_value - operand_2_value;
|
|
break;
|
|
case RegisterArithmeticType_Multiplication:
|
|
res_val = operand_1_value * operand_2_value;
|
|
break;
|
|
case RegisterArithmeticType_LeftShift:
|
|
res_val = operand_1_value << operand_2_value;
|
|
break;
|
|
case RegisterArithmeticType_RightShift:
|
|
res_val = operand_1_value >> operand_2_value;
|
|
break;
|
|
case RegisterArithmeticType_LogicalAnd:
|
|
res_val = operand_1_value & operand_2_value;
|
|
break;
|
|
case RegisterArithmeticType_LogicalOr:
|
|
res_val = operand_1_value | operand_2_value;
|
|
break;
|
|
case RegisterArithmeticType_LogicalNot:
|
|
res_val = ~operand_1_value;
|
|
break;
|
|
case RegisterArithmeticType_LogicalXor:
|
|
res_val = operand_1_value ^ operand_2_value;
|
|
break;
|
|
case RegisterArithmeticType_None:
|
|
res_val = operand_1_value;
|
|
break;
|
|
}
|
|
|
|
|
|
/* Apply bit width. */
|
|
switch (cur_opcode.perform_math_reg.bit_width) {
|
|
case 1:
|
|
res_val = static_cast<u8>(res_val);
|
|
break;
|
|
case 2:
|
|
res_val = static_cast<u16>(res_val);
|
|
break;
|
|
case 4:
|
|
res_val = static_cast<u32>(res_val);
|
|
break;
|
|
case 8:
|
|
res_val = static_cast<u64>(res_val);
|
|
break;
|
|
}
|
|
|
|
/* Save to register. */
|
|
this->registers[cur_opcode.perform_math_reg.dst_reg_index] = res_val;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
} |