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49 lines
1.8 KiB
C
49 lines
1.8 KiB
C
#ifndef EXOSPHERE_INTERRUPT_H
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#define EXOSPHERE_INTERRUPT_H
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#include <stdint.h>
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#include "mmu.h"
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/* Exosphere driver for the Tegra X1 GIC-400 registers. */
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#define MAX_REGISTERED_INTERRUPTS 4
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#define INTERRUPT_ID_SECURITY_ENGINE 0x5A
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#define GICD_BASE (mmio_get_device_address(MMIO_DEVID_GICD))
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#define GICC_BASE (mmio_get_device_address(MMIO_DEVID_GICC))
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#define GICD_IGROUPR ((volatile uint32_t *)(GICD_BASE + 0x080ULL))
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#define GICD_ISENABLER ((volatile uint32_t *)(GICD_BASE + 0x100ULL))
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#define GICD_ISPENDR ((volatile uint32_t *)(GICD_BASE + 0x200ULL))
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#define GICD_IPRIORITYR ((volatile uint8_t *)(GICD_BASE + 0x400ULL))
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#define GICD_ITARGETSR ((volatile uint8_t *)(GICD_BASE + 0x800ULL))
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#define GICD_ICFGR ((volatile uint32_t *)(GICD_BASE + 0xC00ULL))
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#define GICC_CTLR (*((volatile uint32_t *)(GICC_BASE + 0x0000ULL)))
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#define GICC_PMR (*((volatile uint32_t *)(GICC_BASE + 0x0004ULL)))
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#define GICC_BPR (*((volatile uint32_t *)(GICC_BASE + 0x0008ULL)))
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#define GICC_IAR (*((volatile uint32_t *)(GICC_BASE + 0x000CULL)))
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#define GICC_EOIR (*((volatile uint32_t *)(GICC_BASE + 0x0010ULL)))
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#define GIC_PRI_HIGHEST_SECURE 0x00
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#define GIC_PRI_HIGHEST_NONSECURE 0x80
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#define GIC_GROUP_SECURE 0
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#define GIC_GROUP_NONSECURE 1
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/* To be called by FIQ handler. */
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void handle_registered_interrupt(void);
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/* Initializes the GIC. TODO: This must be called during wakeup. */
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void intr_initialize_gic(void);
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void intr_register_handler(unsigned int id, void (*handler)(void));
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void intr_set_group(unsigned int id, int group);
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void intr_set_pending(unsigned int id);
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void intr_set_priority(unsigned int id, uint8_t priority);
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void intr_set_cpu_mask(unsigned int id, uint8_t mask);
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void intr_set_edge_level(unsigned int id, int edge_level);
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void intr_set_enabled(unsigned int id, int enabled);
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#endif |