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https://github.com/Atmosphere-NX/Atmosphere.git
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262 lines
8.8 KiB
C
262 lines
8.8 KiB
C
#ifndef EXOSPHERE_MMU_H
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#define EXOSPHERE_MMU_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include "utils.h"
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#ifndef MMU_GRANULE_TYPE
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#define MMU_GRANULE_TYPE 0 /* 0: 4KB, 1: 64KB, 2: 16KB. The Switch always uses a 4KB granule size. */
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#endif
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#if MMU_GRANULE_TYPE == 0
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#define MMU_Lx_SHIFT(x) (12 + 9 * (3 - (x)))
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#define MMU_Lx_MASK(x) (BIT(9) - 1)
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#elif MMU_GRANULE_TYPE == 1
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/* 64 KB, no L0 here */
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#define MMU_Lx_SHIFT(x) (16 + 13 * (3 - (x)))
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#define MMU_Lx_MASK(x) ((x) == 1 ? (BIT(5) - 1) : (BIT(13) - 1))
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#elif MMU_GRANULE_TYPE == 2
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#define MMU_Lx_SHIFT(x) (14 + 11 * (3 - (x)))
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#define MMU_Lx_MASK(x) ((x) == 0 ? 1 : (BIT(11) - 1))
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#endif
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/*
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* The following defines are adapted from uboot:
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*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define MMU_MT_DEVICE_NGNRNE 0
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#define MMU_MT_DEVICE_NGNRE 1
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#define MMU_MT_DEVICE_GRE 2
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#define MMU_MT_NORMAL_NC 3
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#define MMU_MT_NORMAL 4
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/*
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* Hardware page table definitions.
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*
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*/
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#define MMU_PTE_TYPE_MASK 3
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#define MMU_PTE_TYPE_FAULT 0
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#define MMU_PTE_TYPE_TABLE 3
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#define MMU_PTE_TYPE_BLOCK 1
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/* L3 only */
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#define MMU_PTE_TYPE_PAGE 1
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#define MMU_PTE_TABLE_PXN BITL(59)
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#define MMU_PTE_TABLE_XN BITL(60)
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#define MMU_PTE_TABLE_AP BITL(61)
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#define MMU_PTE_TABLE_NS BITL(63)
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/*
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* Block
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*/
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#define MMU_PTE_BLOCK_MEMTYPE(x) ((x) << 2)
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#define MMU_PTE_BLOCK_NS BIT(5)
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#define MMU_PTE_BLOCK_NON_SHAREABLE (0 << 8)
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#define MMU_PTE_BLOCK_OUTER_SHAREABLE (2 << 8)
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#define MMU_PTE_BLOCK_INNER_SHAREBLE (3 << 8)
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#define MMU_PTE_BLOCK_AF BIT(10)
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#define MMU_PTE_BLOCK_NG BIT(11)
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#define MMU_PTE_BLOCK_PXN BITL(53)
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#define MMU_PTE_BLOCK_UXN BITL(54)
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#define MMU_PTE_BLOCK_XN MMU_PTE_BLOCK_UXN
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/*
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* AP[2:1]
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*/
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#define MMU_AP_PRIV_RW (0 << 6)
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#define MMU_AP_RW (1 << 6)
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#define MMU_AP_PRIV_RO (2 << 6)
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#define MMU_AP_RO (3 << 6)
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/*
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* S2AP[2:1] (for stage2 translations; secmon doesn't use it)
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*/
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#define MMU_S2AP_NONE (0 << 6)
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#define MMU_S2AP_RO (1 << 6)
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#define MMU_S2AP_WO (2 << 6)
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#define MMU_S2AP_RW (3 << 6)
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/*
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* AttrIndx[2:0]
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*/
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#define MMU_PMD_ATTRINDX(t) ((t) << 2)
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#define MMU_PMD_ATTRINDX_MASK (7 << 2)
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/*
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* TCR flags.
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*/
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#define TCR_T0SZ(x) ((64 - (x)) << 0)
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#define TCR_IRGN_NC (0 << 8)
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#define TCR_IRGN_WBWA (1 << 8)
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#define TCR_IRGN_WT (2 << 8)
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#define TCR_IRGN_WBNWA (3 << 8)
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#define TCR_IRGN_MASK (3 << 8)
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#define TCR_ORGN_NC (0 << 10)
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#define TCR_ORGN_WBWA (1 << 10)
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#define TCR_ORGN_WT (2 << 10)
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#define TCR_ORGN_WBNWA (3 << 10)
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#define TCR_ORGN_MASK (3 << 10)
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#define TCR_NOT_SHARED (0 << 12)
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#define TCR_SHARED_OUTER (2 << 12)
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#define TCR_SHARED_INNER (3 << 12)
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#define TCR_TG0_4K (0 << 14)
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#define TCR_TG0_64K (1 << 14)
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#define TCR_TG0_16K (2 << 14)
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#define TCR_EPD1_DISABLE BIT(23)
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#define TCR_EL1_RSVD BIT(31)
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#define TCR_EL2_RSVD (BIT(31) | BIT(23))
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#define TCR_EL3_RSVD (BIT(31) | BIT(23))
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static inline void mmu_init_table(uintptr_t *tbl, size_t num_entries) {
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for(size_t i = 0; i < num_entries; i++) {
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tbl[i] = MMU_PTE_TYPE_FAULT;
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}
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}
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/*
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All the functions below assume base_addr is valid.
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They do not invalidate the TLB, which must be done separately.
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*/
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static inline unsigned int mmu_compute_index(unsigned int level, uintptr_t base_addr) {
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return (base_addr >> MMU_Lx_SHIFT(level)) & MMU_Lx_MASK(level);
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}
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static inline void mmu_map_table(unsigned int level, uintptr_t *tbl, uintptr_t base_addr, uintptr_t *next_lvl_tbl_pa, uint64_t attrs) {
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tbl[mmu_compute_index(level, base_addr)] = (uintptr_t)next_lvl_tbl_pa | attrs | MMU_PTE_TYPE_TABLE;
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}
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static inline void mmu_map_block(unsigned int level, uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, uint64_t attrs) {
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tbl[mmu_compute_index(level, base_addr)] = phys_addr | attrs | MMU_PTE_BLOCK_AF | MMU_PTE_TYPE_BLOCK;
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}
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static inline void mmu_map_page(uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, uint64_t attrs) {
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tbl[mmu_compute_index(3, base_addr)] = phys_addr | attrs | MMU_PTE_BLOCK_AF | MMU_PTE_TYPE_PAGE;
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}
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static inline void mmu_unmap(unsigned int level, uintptr_t *tbl, uintptr_t base_addr) {
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tbl[mmu_compute_index(level, base_addr)] = MMU_PTE_TYPE_FAULT;
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}
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static inline void mmu_map_block_range(unsigned int level, uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, size_t size, uint64_t attrs) {
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size = (size >> MMU_Lx_SHIFT(level)) << MMU_Lx_SHIFT(level);
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for(size_t offset = 0; offset < size; offset += MMU_Lx_SHIFT(level)) {
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mmu_map_block(level, tbl, base_addr + offset, phys_addr + offset, attrs);
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}
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}
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static inline void mmu_map_page_range(uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, size_t size, uint64_t attrs) {
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size = (size >> MMU_Lx_SHIFT(3)) << MMU_Lx_SHIFT(3);
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for(size_t offset = 0; offset < size; offset += MMU_Lx_SHIFT(3)) {
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mmu_map_page(tbl, base_addr + offset, phys_addr + offset, attrs);
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}
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}
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static inline void mmu_unmap_range(unsigned int level, uintptr_t *tbl, uintptr_t base_addr, uintptr_t phys_addr, size_t size) {
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size = (size >> MMU_Lx_SHIFT(level)) << MMU_Lx_SHIFT(level);
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for(size_t offset = 0; offset < size; offset += MMU_Lx_SHIFT(level)) {
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mmu_unmap(level, tbl, base_addr + offset);
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}
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}
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/* Switch specific stuff */
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static const struct {
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uintptr_t pa;
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size_t size;
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bool is_secure;
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} devices[] =
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{
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{ 0x50041000, 0x1000, true }, /* ARM Interrupt Distributor */
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{ 0x50042000, 0x2000, true }, /* Interrupt Controller Physical CPU interface */
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{ 0x70006000, 0x1000, false }, /* UART-A */
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{ 0x60006000, 0x1000, false }, /* Clock and Reset */
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{ 0x7000E000, 0x1000, true }, /* RTC, PMC */
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{ 0x60005000, 0x1000, true }, /* TMRs, WDTs */
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{ 0x6000C000, 0x1000, true }, /* System Registers */
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{ 0x70012000, 0x2000, true }, /* SE */
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{ 0x700F0000, 0x1000, true }, /* SYSCTR0 */
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{ 0x70019000, 0x1000, true }, /* MC */
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{ 0x7000F000, 0x1000, true }, /* FUSE (0x7000F800) */
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{ 0x70000000, 0x4000, true }, /* MISC */
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{ 0x60007000, 0x1000, true }, /* Flow Controller */
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{ 0x40002000, 0x1000, true }, /* iRAM-A */
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{ 0x7000D000, 0x1000, true }, /* I2C-5,6 - SPI 2B-1 to 4 */
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{ 0x6000D000, 0x1000, true }, /* GPIO-1 - GPIO-8 */
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{ 0x7000C000, 0x1000, true }, /* I2C-I2C4 */
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{ 0x6000F000, 0x1000, true }, /* Exception vectors */
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};
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#define MMIO_DEVID_GICD 0
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#define MMIO_DEVID_ICC 1
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#define MMIO_DEVID_UART_A 2
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#define MMIO_DEVID_CLKRST 3
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#define MMIO_DEVID_RTC_PMC 4
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#define MMIO_DEVID_TMRs_WDTs 5
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#define MMIO_DEVID_SYSREGS 6
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#define MMIO_DEVID_SE 7
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#define MMIO_DEVID_SYSCTR0 8
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#define MMIO_DEVID_MC 9
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#define MMIO_DEVID_FUSE 10
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#define MMIO_DEVID_MISC 11
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#define MMIO_DEVID_FLOWCTRL 12
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#define MMIO_DEVID_NXBOOTLOADER_MAILBOX 13
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#define MMIO_DEVID_I2C56_SPI2B 14
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#define MMIO_DEVID_GPIO 15
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#define MMIO_DEVID_DTV_I2C234 16
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#define MMIO_DEVID_EXCEPTION_VECTORS 17
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#ifndef MMIO_USE_IDENTIY_MAPPING
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#define MMIO_BASE 0x1F0080000ull
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static inline uintptr_t mmio_get_device_address(unsigned int device_id) {
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size_t offset = 0;
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for(unsigned int i = 0; i < device_id; i++) {
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offset += devices[i].size;
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offset += 0x1000; /* guard page */
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}
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return MMIO_BASE + offset;
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}
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#else
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static inline uintptr_t mmio_get_device_address(unsigned int devid) {
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return devices[devid];
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}
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#endif
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static inline void mmio_map_all_devices(uintptr_t *mmu_l3_tbl) {
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static const uint64_t secure_device_attributes = MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_INNER_SHAREBLE | MMU_PTE_BLOCK_MEMTYPE(1);
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static const uint64_t device_attributes = MMU_PTE_TABLE_NS | secure_device_attributes;
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for(size_t i = 0, offset = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
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uint64_t attributes = devices[i].is_secure ? secure_device_attributes : device_attributes;
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mmu_map_page_range(mmu_l3_tbl, MMIO_BASE + offset, devices[i].pa, devices[i].size, attributes);
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offset += devices[i].size;
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offset += 0x1000; /* insert guard page */
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}
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}
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static inline void mmio_unmap_all_devices(uintptr_t *mmu_l3_tbl) {
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for(size_t i = 0, offset = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
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mmu_unmap_range(3, mmu_l3_tbl, MMIO_BASE + offset, devices[i].size);
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offset += devices[i].size;
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offset += 0x1000; /* insert guard page */
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}
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}
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#endif
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