mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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130 lines
4.4 KiB
C++
130 lines
4.4 KiB
C++
/*
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* Copyright (c) 2018-2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stratosphere/reg.hpp>
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#include "gpio_utils.hpp"
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namespace ams::gpio {
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namespace {
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/* Pull in GPIO map definitions. */
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#include "gpio_map.inc"
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constexpr u32 PhysicalBase = 0x6000D000;
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/* Globals. */
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bool g_initialized_gpio_vaddr = false;
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uintptr_t g_gpio_vaddr = 0;
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/* Helpers. */
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inline u32 GetPadDescriptor(u32 gpio_pad_name) {
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AMS_ASSERT(gpio_pad_name < PadNameMax);
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return Map[gpio_pad_name];
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}
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uintptr_t GetBaseAddress() {
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if (!g_initialized_gpio_vaddr) {
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g_gpio_vaddr = dd::GetIoMapping(PhysicalBase, os::MemoryPageSize);
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g_initialized_gpio_vaddr = true;
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}
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return g_gpio_vaddr;
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}
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}
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u32 Configure(u32 gpio_pad_name) {
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uintptr_t gpio_base_vaddr = GetBaseAddress();
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/* Fetch this GPIO's pad descriptor */
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const u32 gpio_pad_desc = GetPadDescriptor(gpio_pad_name);
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/* Discard invalid GPIOs */
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if (gpio_pad_desc == InvalidPadName) {
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return InvalidPadName;
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}
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/* Convert the GPIO pad descriptor into its register offset */
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u32 gpio_reg_offset = (((gpio_pad_desc << 0x03) & 0xFFFFFF00) | ((gpio_pad_desc >> 0x01) & 0x0C));
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/* Extract the bit and lock values from the GPIO pad descriptor */
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u32 gpio_cnf_val = ((0x01 << ((gpio_pad_desc & 0x07) | 0x08)) | (0x01 << (gpio_pad_desc & 0x07)));
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/* Write to the appropriate GPIO_CNF_x register (upper offset) */
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reg::Write(gpio_base_vaddr + gpio_reg_offset + 0x80, gpio_cnf_val);
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/* Do a dummy read from GPIO_CNF_x register (lower offset) */
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gpio_cnf_val = reg::Read(gpio_base_vaddr + gpio_reg_offset + 0x00);
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return gpio_cnf_val;
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}
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u32 SetDirection(u32 gpio_pad_name, GpioDirection dir) {
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uintptr_t gpio_base_vaddr = GetBaseAddress();
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/* Fetch this GPIO's pad descriptor */
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const u32 gpio_pad_desc = GetPadDescriptor(gpio_pad_name);
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/* Discard invalid GPIOs */
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if (gpio_pad_desc == InvalidPadName) {
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return InvalidPadName;
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}
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/* Convert the GPIO pad descriptor into its register offset */
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u32 gpio_reg_offset = (((gpio_pad_desc << 0x03) & 0xFFFFFF00) | ((gpio_pad_desc >> 0x01) & 0x0C));
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/* Set the direction bit and lock values */
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u32 gpio_oe_val = ((0x01 << ((gpio_pad_desc & 0x07) | 0x08)) | (static_cast<u32>(dir) << (gpio_pad_desc & 0x07)));
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/* Write to the appropriate GPIO_OE_x register (upper offset) */
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reg::Write(gpio_base_vaddr + gpio_reg_offset + 0x90, gpio_oe_val);
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/* Do a dummy read from GPIO_OE_x register (lower offset) */
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gpio_oe_val = reg::Read(gpio_base_vaddr + gpio_reg_offset + 0x10);
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return gpio_oe_val;
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}
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u32 SetValue(u32 gpio_pad_name, GpioValue val) {
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uintptr_t gpio_base_vaddr = GetBaseAddress();
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/* Fetch this GPIO's pad descriptor */
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const u32 gpio_pad_desc = GetPadDescriptor(gpio_pad_name);
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/* Discard invalid GPIOs */
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if (gpio_pad_desc == InvalidPadName) {
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return InvalidPadName;
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}
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/* Convert the GPIO pad descriptor into its register offset */
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u32 gpio_reg_offset = (((gpio_pad_desc << 0x03) & 0xFFFFFF00) | ((gpio_pad_desc >> 0x01) & 0x0C));
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/* Set the output bit and lock values */
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u32 gpio_out_val = ((0x01 << ((gpio_pad_desc & 0x07) | 0x08)) | (static_cast<u32>(val) << (gpio_pad_desc & 0x07)));
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/* Write to the appropriate GPIO_OUT_x register (upper offset) */
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reg::Write(gpio_base_vaddr + gpio_reg_offset + 0xA0, gpio_out_val);
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/* Do a dummy read from GPIO_OUT_x register (lower offset) */
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gpio_out_val = reg::Read(gpio_base_vaddr + gpio_reg_offset + 0x20);
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return gpio_out_val;
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}
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}
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