mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-18 08:11:21 +00:00
f66b41c027
exo2: Implement uncompressor stub and boot code up to Main(). exo2: implement some more init (uart/gic) exo2: implement more of init exo2: improve reg api, add keyslot flag setters exo2: implement se aes decryption/enc exo2: fix bugs in loader stub/mmu mappings exo2: start skeletoning bootconfig/global context types arch: fix makefile flags exo2: implement through master key derivation exo2: implement device master keygen exo2: more init through start of SetupSocSecurity exo2: implement pmc secure scratch management se: implement sticky bit validation libexosphere: fix building for arm32 libexo: fix makefile flags libexo: support building for arm64/arm sc7fw: skeleton binary sc7fw: skeleton a little more sc7fw: implement all non-dram functionality exo2: fix DivideUp error sc7fw: implement more dram code, fix reg library errors sc7fw: complete sc7fw impl. exo2: skeleton the rest of SetupSocSecurity exo2: implement fiq interrupt handler exo2: implement all exception handlers exo2: skeleton the entire smc api, implement the svc invoker exo2: implement rest of SetupSocSecurity exo2: correct slave security errors exo2: fix register definition exo2: minor fixes
117 lines
3.9 KiB
C++
117 lines
3.9 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "sc7fw_util.hpp"
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#include "sc7fw_dram.hpp"
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namespace ams::sc7fw {
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namespace {
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constexpr inline const uintptr_t PMC = secmon::MemoryRegionPhysicalDevicePmc.GetAddress();
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void DisableCrail() {
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/* Wait for CRAIL to be off. */
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while (!reg::HasValue(PMC + APBDEV_PMC_PWRGATE_STATUS, PMC_REG_BITS_ENUM(PWRGATE_STATUS_CRAIL, OFF))) { /* ... */ }
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/* Set CRAIL to be clamped. */
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reg::ReadWrite(PMC + APBDEV_PMC_SET_SW_CLAMP, PMC_REG_BITS_VALUE(SET_SW_CLAMP_CRAIL, 1));
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/* Wait for CRAIL to be clamped. */
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while (!reg::HasValue(PMC + APBDEV_PMC_CLAMP_STATUS, PMC_REG_BITS_ENUM(CLAMP_STATUS_CRAIL, ENABLE))) { /* ... */ }
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/* Spin loop for a short while, to allow time for the clamp to take effect. */
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sc7fw::SpinLoop(10);
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/* Initialize i2c-5. */
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i2c::Initialize(i2c::Port_5);
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/* Disable the voltage to CPU. */
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pmic::DisableVddCpu(fuse::GetRegulator());
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/* Wait 700 microseconds to ensure voltage is disabled. */
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util::WaitMicroSeconds(700);
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}
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void DisableAllInterrupts() {
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/* Disable all interrupts for bpmp in all interrupt controllers. */
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reg::Write(PRI_ICTLR(ICTLR_COP_IER_CLR), ~0u);
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reg::Write(SEC_ICTLR(ICTLR_COP_IER_CLR), ~0u);
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reg::Write(TRI_ICTLR(ICTLR_COP_IER_CLR), ~0u);
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reg::Write(QUAD_ICTLR(ICTLR_COP_IER_CLR), ~0u);
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reg::Write(PENTA_ICTLR(ICTLR_COP_IER_CLR), ~0u);
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reg::Write(HEXA_ICTLR(ICTLR_COP_IER_CLR), ~0u);
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}
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void EnterSc7() {
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/* Disable read buffering and write buffering in the BPMP cache. */
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reg::ReadWrite(AVP_CACHE_ADDRESS(AVP_CACHE_CONFIG), AVP_CACHE_REG_BITS_ENUM(DISABLE_WB, TRUE),
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AVP_CACHE_REG_BITS_ENUM(DISABLE_RB, TRUE));
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/* Ensure the CPU Rail is turned off. */
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DisableCrail();
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/* Disable all interrupts. */
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DisableAllInterrupts();
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/* Save the EMC FSP */
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SaveEmcFsp();
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/* Enable self-refresh for DRAM */
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EnableSdramSelfRefresh();
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/* Enable refresh for all EMC devices. */
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EnableEmcAllSegmentsRefresh();
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/* Enable deep power-down for ddr. */
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EnableDdrDeepPowerDown();
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/* Enable pad sampling during deep sleep. */
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reg::ReadWrite(PMC + APBDEV_PMC_DPD_SAMPLE, PMC_REG_BITS_ENUM(DPD_SAMPLE_ON, ENABLE));
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reg::Read(PMC + APBDEV_PMC_DPD_SAMPLE);
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/* Wait a while for pad sampling to be enabled. */
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sc7fw::SpinLoop(0x128);
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/* Enter deep sleep. */
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reg::ReadWrite(PMC + APBDEV_PMC_DPD_ENABLE, PMC_REG_BITS_ENUM(DPD_ENABLE_ON, ENABLE));
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/* Wait forever until we're asleep. */
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while (true) { /* ... */ }
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}
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}
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void Main() {
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EnterSc7();
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}
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NORETURN void ExceptionHandler() {
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/* Write enable to MAIN_RESET. */
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reg::Write(PMC + APBDEV_PMC_CNTRL, PMC_REG_BITS_ENUM(CNTRL_MAIN_RESET, ENABLE));
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while (true) { /* ... */ }
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}
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}
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namespace ams::diag {
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void AbortImpl() {
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sc7fw::ExceptionHandler();
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}
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}
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